摘要
高速光电信号的时域采集并对其波形瞬态特征进行分析,取样采样得益于等效采样技术,通过触发沿不断延时来重构波形,打破了ADC的速度位宽限制,实现低成本高带宽,同时也提高了测量精度。研究了一种基于FGPA控制高精细延迟线芯片的粗、细延多级脉冲延迟电路,外部输入1 MHz~30 GHz的触发时钟,预分频后,通过PLL(phase locked loop)将同步信号倍频到122~128 MHz,FPGA内部进行计数,产生倍频时钟周期的粗延时,再利用两个10 bit高精密延时线芯片级联,进一步实现了5 ps精细延迟划分。通过粗细延时配合最终实现了范围达到10μs、分辨率5 ps的大动态范围、高分辨率延迟效果。
High-speed optoelectronic signals are collected in the time domain and the transient characteristics of the waveform are analyzed.Sampling sampling benefits from the equivalent sampling technology,which can reconstruct the waveform by triggering the continuous delay,breaking the speed bit width limit of ADC,achieving low cost and high bandwidth,and improving the measurement accuracy.In this paper,a coarse and fine delay multistage pulse delay circuit based on FGPA control of high precision delay line chip is developed.The trigger clock of 1 MHz~30 GHz is input externally.After pre-frequency separation,the synchronization signal is frequency doubling to 122~128 MHz through phase locked loop(PLL).The coarse delay of the double frequency clock cycle is generated,and then two 10 bit high-precision delay line chips are casccasced to further realize the fine delay division of 5 ps.Finally,the large dynamic range and high resolution delay effect of 10μs and 5 ps are achieved through the combination of coarse delay and fine delay.
作者
程亚昊
王志斌
景宁
Cheng Yahao;Wang Zhibin;Jing Ning(School of Instrument and Electronics,North University of China,Taiyuan 030051,China;Center for Microsystem Intergration,North University of China,Taiyuan 030051,China;School of Information and Communication Engineering,North University of China,Taiyuan 030051,China)
出处
《国外电子测量技术》
北大核心
2022年第2期169-172,共4页
Foreign Electronic Measurement Technology
基金
国家自然基金青年基金(62105302)
山西省青年基金(201801D221211)
山西省自然基金(201901D111145)项目资助
关键词
PLL
延时
FPGA
频率测量
信号同步
PLL
delay
FPGA
frequency measurement
signal synchronization
作者简介
程亚昊,硕士研究生,主要研究方向为射频器件测试和微波电路设计。E-mail:1227850089@qq.com
