摘要
绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor,IGBT)器件的最重要参数之一是击穿电压(Breakdown Voltage,BV),影响IGBT器件BV的因素包括:平面工艺PN结扩散终端、界面电荷、杂质在Si、SiO2中具有不同分凝系数等。其中影响IGBT器件耐压能力的重要因素是芯片终端结构的设计,终端区耗尽层边界的曲率半径制约了BV的提升,为了能够减少曲率效应和增大BV,可以采取边缘终端技术。通过Sentaurus TCAD计算机仿真软件,采取横向变掺杂(Variable Lateral Doping,VLD)技术,设计了一款650 V IGBT功率器件终端,在VLD区域利用掩膜技术刻蚀掉一定的硅,形成浅凹陷结构。仿真结果表明,这一结构实现了897 V的耐压,终端长度为256μm,与同等耐压水平的场限环终端结构相比,终端长度减小了19.42%,且最大表面电场强度为1.73×10^(5)V/cm,小于硅的临界击穿电场强度(2.5×10^(5)V/cm);能在极大降低芯片面积的同时提高BV,并且提升了器件主结的耐压能力。此外,工艺步骤无增加,与传统器件制造工艺相兼容。
Breakdown voltage(BV)is one of the most important parameters of IGBT(Insulated Gate Bipolar Transistor)devices,which can be affected by planar process of PN junction diffusion terminals,interface charges,and different coagulation coefficients in Si and SiO2.And the design of the chip terminal structure is one of the important factors affecting the withstand voltage capability.However,improvement of BV is largely restricted by the curvature radius of the depletion region boundary in the terminal area.Here edge termination technology can was used to reduce the curvature effect and increase the BV.This article used Sentaurus TCAD computer simulation software and adopted Variable Lateral Doping(VLD)technology to design a 650 V IGBT power device terminal,where partial silicon was etched away in the VLD region by using mask technique to form a shallow concave structure.The simulation results show that this structure achieves a withstand voltage of 897 V with a terminal length of 256μm,which is 19.42%less than the field limiting ring terminal structure at the same level of withstand voltage.The maximum surface electric field strength is 1.73×10^(5)V/cm,which is less than the critical breakdown electric field strength of silicon(2.5×10^(5)V/cm).The BV can be increased while greatly reducing the chip area and improving the withstand voltage of the device's main junction.In addition,the fabrication process is not affected,and it is compatible with traditional manufacturing processes for devices.
作者
高兰艳
冯全源
GAO Lanyan;FENG Quanyuan(Institute of Microelectronics,Southwest Jiaotong University,Chengdu 611756,China)
出处
《电子元件与材料》
CAS
北大核心
2024年第1期61-66,共6页
Electronic Components And Materials
基金
国家自然科学基金(62090012)
四川省重点研发项目(2023YFG0004)。
作者简介
通信作者:冯全源,教授,博士,主要从事功率半导体、集成电路设计等方向的研究。E-mail:fengquanyuan@163.com。
