摘要
给出了以高性能FPGA和DSP为核心实现的并行信号采集和万兆高速传输系统,通过5片ADC芯片的分时采集和误差校正实现了2.5Gsps多通道信号高精度并行采集,基于交换路由芯片实现了万兆串行RapidIO互连.基于FPGA逻辑实现以Farrow结构分数延时滤波器为核心的定时误差校正算法;配置DSP高速串口、FPGA GTX收发器和路由芯片实现了可扩展的高速通信机制,优化实现了高性能DSP的信号处理.
This paper presents an embedded Multi-channel Parallel Signal Acquisition and 10G High-speed Transmission System using TI TMS320C6455 DSP and Virtex5 FPGA ,which can achieve 2 .5 Gsps five-channel-time-interleaved Parallel Signal Acquisition and 10G RapidIO routing .The sample-timing error algorithm of signal reconstruction based Farrow filter is realized in FPGA ,and by configure the high-speed serial port and the routing chip the high-speed communication mechanism can be extended .By analyzing the hardware architecture and resource of embedded platform ,the efficient DSP-based compute is described .
出处
《微电子学与计算机》
CSCD
北大核心
2014年第6期30-35,共6页
Microelectronics & Computer
