摘要
不精确的广义门电路可靠性映射到门级或高层应用时误差容易因规模效应等而被过度放大导致结果不可靠.本文选择了在门级电路可靠性精确评估中得到有效验证的PTM模型用以精确计算晶体管级广义门电路的结构可靠性;分析了晶体管级广义门电路结构的逻辑抽象并转换成了功能一致的门级电路结构的逻辑抽象形式;提取了电路各组成单元的故障点及主要故障模式,并构建了与之相对应的面向故障的概率转移矩阵;依据各组成单元间的串并联特点,在有考虑输入信号故障的情况下,通过门级PTM方法的运算法则计算得到了晶体管级广义门电路的结构可靠性.在典型的CMOS广义门电路上的实验结果验证了本文所提方法的有效性,还分析了广义门电路的可靠性与其各主要类型故障之间的关系,并获得了一些有意义的结果.
When the imprecise reliability of generalized gates is applied to the gate-level or high-level circuits, the errors could be easily over-enlarged for the scale effect and other reasons, which leads to unreliable results. In this paper, the PTM model, which the effectiveness was proved by accurate gate-level circuit reliability estimation, was chosen to accurately calculate the structure reliability of generalized gates at the transistor-level; the structure logistic abstract of transistor-level generalized gates is analyzed and transformed into the style of gate-level structure logistic abstract having the same function with the pre-transform one; the failure points of circuit components and the main fault modes are extra,ted, and the corresponding probabilistic transfer matrixes oriented to faults are constructed; according to the characteristics of series-parallel circuit components, the structure reliabilities of transistor-level generalized gates are calculated by the gate-level PTM method under the fault conditions on input signals. Simulation results for typical generalized gates demonstrate the effectiveness of the proposed method; furthermore, the relation between generalized gates reliability and these main types faults is analyzed, and some interesting results are got.
出处
《中国科学：信息科学》
CSCD
2014年第10期1226-1238,共13页
Scientia Sinica(Informationis)
基金
国家自然科学基金(批准号:61363002
60903033
61432017)资助项目
作者简介
通信作者．E—mail：xiaojiexqj@gmail．com. XIAO Jie was born in 1984. He received the Ph.D. degree in computer systems architecture from Tongji University, Shanghai, China, in 2013. Currently, he is a teacher at Zhejiang University of Technology. His current research interests include dependable and fault-tolerant computing.
JIANG JianHui was born in 1964. He received the Ph.D. degree in computer science and technology in Shanghai Railway University, Shanghai, China, in 1999. Currently, he is a professor and Ph.D. supervisor in school of Software Engineering, Tongji University. His current research interests include dependable system and network, software reliability engineering, and VLSI/SoC fault-tolerance and test.
LIANG JiaRong was born in 1966. He received the Ph.D. degree in institute of automation from South China University of Technology, Guangzhou, China, in 1998. Currently, he is a professor and Ph.D. supervisor in school of computer and electronic information, Guangxi University. His research interests include parallel and distributed, wireless sensor network and network reliability analysis.
