摘要
在传统集成电路(IC)的低功耗设计方法基础上,提出3种低功耗技术,并实现无线传感网传感器节点,作为实例验证。在系统级,提出联合编译技术的优化策略以及为无线传感网提供特殊低功耗模式的硬件架构。在电路级,基于集成电路算子设计方法学,考虑到在算法映射阶段时钟布局,提出时钟算子。以上技术均通过一个无线传感网传感器节点的低功耗设计实例来验证。测试结果显示,使用新提出的3种方法,在深度睡眠模式下,传感器节点芯片功耗为167μW,板级功耗可以达到1.035 mW。
Base on traditional integrated circuit （[C） low power methods, the authors propose three low power technologies for further research and take an implementation of WSN sensor node as an example. At system level, the authors present an optimum scheme combined with compiling technology and a hardware structure which provides special low power modes for WSN. At circuit level, considering clock placement in arithmetic mapping phase, clock operators in collaboration with IC operator design methodology （ODM） is proposed. A low power design of WSN sensor node is implemented to verify the low power technologies presented above. The testing results show that WSN sensor node consumes 167 μW at chip level and PCB system 1.035 mW at PCB system level in deep sleep mode by the three methods.
出处
《北京大学学报（自然科学版）》
EI
CAS
CSCD
北大核心
2014年第4期664-674,共11页
Acta Scientiarum Naturalium Universitatis Pekinensis
关键词
无线传感网
低功耗设计
集成电路
wireless sensor network
low power design
integrated circuit
作者简介
E-mail：zhouyh@eda．ac．n
