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动态可重构FPGA布局算法

A Layout Algorithm for Dynamically Reconfigurable FPGA
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摘要 SRAM(Static Random Access Memory)型FPGA凭借其动态结构调整的灵活性等特点,被广泛应用于工业领域。针对动态可重构功能单元的布局问题,分析了模拟退火解决方案的局限性,提出了基于电路分层划分和时延驱动的在线布局算法。算法首先按最小分割原则将电路划分为一定数目的层,然后按自顶向下的原则在芯片的每一层中布局划分出的层,同时保证电路关键路径的延时最小。实验结果表明,所述算法在时延、线长和运行时间方面均优于VPR算法。 Due to their flexibility in dynamic structural adjustment,Static Random Access Memory ( SRAM) based Field Programmable Gate Arrays ( FPGAs) are widely applied in industry and other fields .Aimed at the layout problem of modules on the reconfigurable functional unit,a hierarchical circuit partitioning-based timing-driven placement algorithm was proposed based on analysis to the limitation of the simulated annealing algorithm.The circuit was first divided into limited number of tiers based on principle of minimum cut,and then the layout of each tier was implemented according to top-down principle .The algorithm can also attain the minimum critical path delay .Experimental results show that:compared VPR algorithm,the proposed algorithm achieves better results in delay,wire-length and runtime .
出处 《电光与控制》 北大核心 2014年第4期77-80,共4页 Electronics Optics & Control
关键词 大规模集成电路 动态可重构 布局 FIELD PROGRAMMABLE GATE ARRAY ( FPGA) FPGA LSIC Dynamic Reconfiguration placement
作者简介 张寒(1982-),女,黑龙江哈尔滨人,硕士,工程师,研究方向为动态可重构系统的设计与测试。
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