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时间交替采样系统的误差测量与FPGA实现 被引量:7

Measurement and calibration of mismatched errors in multi-chip ADC time-interleaved systems
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摘要 时间交替采样结构是模数转换中提高采样率的1种有效方法。但由于器件工艺限制,每个通道的不一致性会引入通道失配误差,而这些误差会导致信号存在较大的杂散分量,将会严重影响ADC的性能。通道误差包括增益误差、时间误差、偏置误差。提出了一种频域的方法通过对单路采样信号做快速傅里叶变换并由固定位置方法找出误差的频域值,对此频域值做相应数学变换得到3种误差并且对这种方法进行了FPGA仿真实现,通过ISE仿真2路AD拼接系统的误差测量,验证了其有效性。 Time-interleaved sampling system is a efficient method to increase the sampling rate of the analog to digital converter(ADC) system.But because of the limits of the manufacture technics,the mismatch between different channels will cause the mismatch errors.These errors will produce new noises in signals and affect the performence of ADC system.Channel mismatch error includs gain error,time error and offset error.In this paper,a method based on fft for single signal to Calculation the mismatch errors is presented.And the ISE simulation results for 2 channels Time-interleaved sampling system are given to prove the availability of this method.
出处 《电子测量技术》 2011年第3期54-56,共3页 Electronic Measurement Technology
关键词 时间交替采样 通道失配误差 模数转换 analog to digital converter channel mismatch error time-interleaved sampling
作者简介 朱子翰,2009年于海南大学获得学士学位,现为电子科技大学硕士研究生,主要研究方向为多片时间交替采样技术研究。E—mail:zhuzihan117115@yahoo.com.cn
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  • 1尹亮,周劼,姚军.多片ADC并行采集系统的增益误差补偿[J].现代电子技术,2007,30(17):170-171. 被引量:5
  • 2JR BLACK W C, HODGES D A. Time interleaved con- verter arrays [ M ]. IEEE Journal of Solid-State Circuits, 1980,15 (6) : 1022-1029.
  • 3KUROSAWA N, KOBAYASHI A, MARUYAMA K, et al. Explicit analysis of channel mismatch effects in time-in- terleaved ADC systems [ J ]. IEEE Transactions on Circuits and System I: Fundamental Theory and Applications, 2001,48 ( 3 ) :261-271.
  • 4MANAR E C,BORIS M. Background calibration of time- interleaved data converters [M ]. Springer Science + Busi- ness Media,2012.
  • 5VOGEL C. The impact of combined channel mismatch effects in time-interleaved ADCs [ J ]. IEEE Transactions on Instru- mentation and Measurement ,2005,54( 1 ) :415-427.
  • 6ZHANG P,YE F,YU B,et al. Mixed-signal calibration of sample-time error in time-interleaved ADCs [ J]. Electron- ics Letters, 2011,47 ( 9 ) : 533-535.
  • 7LIU W, CHIU Y. Time-interleaved analog-to-digital con- version with online adaptive equalization [ J ]. IEEE Transactions on Circuits and Systems l:Regular Papers, 2012,59(7) : 1384-1395.
  • 8MATSUNO J, YAMAJI T, FURUTA M, et al. All-digital background calibration technique for time-interleaved ADC using pseudo aliasing signal [ C ]. IEEE International Sym- posium on Circuits and System ( ISCAS ), IEEE, 2012 : 1050-1053.
  • 9ZOU Y X, ZHANG S L, LIM Y C, et al. Timing mismatch compensation in time-interleaved ADCs based on multi- channel Lagrange polynomial interpolation [ J ]. IEEE Transactions on Instrumentation and Measurement,2011, 60(4) :1123-1131.
  • 10LAW C H, HURST P J,LEWIS S H. A four-channel time- interleaved ADC with digital calibration of interchannel timing and memory errors[ J]. IEEE Journal of Solid-State Circuits ,2010,45 (10) :2091-2103.

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