摘要
在数字电路设计中,经常会遇到分频器的设计问题。而设计等占空比分频器的关键是构造半整数分频器。简要介绍等占空比分频器的构成原理,提出了用CPLD实现等占空比分频的方法,并给出了偶数、奇数等占空比分频器的原理电路,运用Max+PlusⅡ的图形输入法对电路进行了仿真。同时,用VHDL语言对等占空比分频器的主体———计数器的结构进行了描述,并给出了Max+PlusⅡ的波形仿真输出。
In digital circuit design, we always encounter the frequency- divider scheme. The key way for designing out half duty cycle frequency - divider is the construction of half - integer frequency - divider. This paper briefly introduces the principle of half duty cycle frequency - divider, bringings forward the method of how to divide frequency with half duty cycle way using CPLD,and giving the prototype circuit of half duty cycle frequency- divider with even/odd number. Consequently, the simulation circuit with graphics input way in Max＋Plus Ⅱ is realized. In other way,how to construct with VHDL the main part of half duty cycle frequency divider the counter is described,and accordingly the output wave of VHDL in Max＋Plus Ⅱ simulation environment is presented.
出处
《现代电子技术》
2006年第24期25-26,共2页
Modern Electronics Technique
关键词
占空比
分频器
等占空比分频器
半整数分频器
VHDL
duty cycle
frequency divider
half duty cycle frequency divider
half integer frequency divider
VHDL
作者简介
邓玉元,女，1964年出生，湖南益阳人，副教授。主要从事数字电子技术教学工作。
