摘要
以CDF9/7小波为例构造了一种二维DWT变换的高效VLSI结构。采用改进的提升算法,减少了关键路径上的延时。把乘法器系数表示为CSD形式,将乘法优化为最少的移位加操作。提出了一种行变换和列变换同时进行的方法和实现结构,并且整个结构采用流水线处理。通过VHDL的行为级仿真,得到的数据和软件仿真的结果相同,证明了该结构的正确性。和其它结构相比,该结构处理速度更快,并且硬件利用率可达100%。
An efficient VI.SI architecture for two-dimension DWT is proposed and illustrated in detail for the CDF9/7 wavelet transform. The improved lifting scheme is adopted to reduce the critical path delay. Coefficients of the multipliers are transformed into CSD forms and then the multiplications are substituted by shift-add operations. The row transform and column transform are running simultaneously and pipeline design is used to optimize the architecture. This architecture is implemented through behavioral VHDL. The results are identical with those of the software simulation, and thus the validity of this architecture .is proved. Compared with other architectures, this one has the advantages of faster computation time and almost 100% hardware utilization.
出处
《国防科技大学学报》
EI
CAS
CSCD
北大核心
2005年第6期48-52,共5页
Journal of National University of Defense Technology
基金
国家自然科学基金资助项目(50277010)
高校博士点基金资助项目(20020532016)
关键词
提升算法
小波变换
二维DWT
VLSI
并行结构
lifting scheme
wavelet transform
two-dimensional DWT
VLSI
parallel architecture
作者简介
康志伟（1962-），男，副教授。
