A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral com...A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral component interconnect(PCI)board with an Xilinx Virtex xcv2000E field programmable gate array(FPGA).To improve the quality of the evolved circuits,the VRA works through a two-stage evolution: finding a functional circuit and minimizing the number of logic gates used in a feasible circuit.To optimize the algorithm performance in the two-stage evolutionary process and set free the user from the time-consuming process of mutation parameter tuning,a self-adaptive mutation rate control(SAMRC)scheme is introduced.In the evolutionary process,the mutation rate control parameters are encoded as additional genes in the chromosome and also undergo evolutionary operations.The efficiency of the proposed methodology is tested with the evolutions of a 4-bit even parity function,a 2-bit multiplier,and a 3-bit multiplier.The obtained results demonstrate that our scheme improves the evolutionary design of combinational logic circuits in terms of quality of the evolved circuit as well as the computational effort,when compared to the existing evolvable hardware approaches.展开更多
传统风电机组虚拟惯性控制的惯性时间常数较大,虽抑制了频率变化率(Rate of Change of Frequency,ROCOF),但也阻碍了频率的恢复。文章提出了一种风电机组自适应虚拟惯性控制,该控制在频率扰动初期能够提供适当的虚拟惯性支撑,同时在频...传统风电机组虚拟惯性控制的惯性时间常数较大,虽抑制了频率变化率(Rate of Change of Frequency,ROCOF),但也阻碍了频率的恢复。文章提出了一种风电机组自适应虚拟惯性控制,该控制在频率扰动初期能够提供适当的虚拟惯性支撑,同时在频率恢复期间加快频率恢复。首先,文章控制策略在频率跌落或者上升阶段,根据ROCOF的最大值,自适应计算出虚拟惯性时间常数。该值一直保持到ROCOF的极性发生变化,切换至根据ROCOF计算出的虚拟惯性时间常数,此时的ROCOF较小,虚拟惯性时间常数趋于零。故在频率恢复阶段,风电机组退出虚拟惯性支撑,从而帮助频率加快恢复。在PSCAD/EMTDC中搭建仿真算例,仿真结果,表明文章所提控制策略能够提供虚拟惯性支撑和加快扰动后频率恢复。展开更多
基金Projects(61203308,61309014)supported by the National Natural Science Foundation of China
文摘A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral component interconnect(PCI)board with an Xilinx Virtex xcv2000E field programmable gate array(FPGA).To improve the quality of the evolved circuits,the VRA works through a two-stage evolution: finding a functional circuit and minimizing the number of logic gates used in a feasible circuit.To optimize the algorithm performance in the two-stage evolutionary process and set free the user from the time-consuming process of mutation parameter tuning,a self-adaptive mutation rate control(SAMRC)scheme is introduced.In the evolutionary process,the mutation rate control parameters are encoded as additional genes in the chromosome and also undergo evolutionary operations.The efficiency of the proposed methodology is tested with the evolutions of a 4-bit even parity function,a 2-bit multiplier,and a 3-bit multiplier.The obtained results demonstrate that our scheme improves the evolutionary design of combinational logic circuits in terms of quality of the evolved circuit as well as the computational effort,when compared to the existing evolvable hardware approaches.
文摘传统风电机组虚拟惯性控制的惯性时间常数较大,虽抑制了频率变化率(Rate of Change of Frequency,ROCOF),但也阻碍了频率的恢复。文章提出了一种风电机组自适应虚拟惯性控制,该控制在频率扰动初期能够提供适当的虚拟惯性支撑,同时在频率恢复期间加快频率恢复。首先,文章控制策略在频率跌落或者上升阶段,根据ROCOF的最大值,自适应计算出虚拟惯性时间常数。该值一直保持到ROCOF的极性发生变化,切换至根据ROCOF计算出的虚拟惯性时间常数,此时的ROCOF较小,虚拟惯性时间常数趋于零。故在频率恢复阶段,风电机组退出虚拟惯性支撑,从而帮助频率加快恢复。在PSCAD/EMTDC中搭建仿真算例,仿真结果,表明文章所提控制策略能够提供虚拟惯性支撑和加快扰动后频率恢复。
