A study on the zero-forcing beamforming （ZFBF） scheme with antenna selection at user terminals in downlink multi-antenna multi-user systems is presented. Simulation results show that the proposed ZFBF scheme with re...A study on the zero-forcing beamforming （ZFBF） scheme with antenna selection at user terminals in downlink multi-antenna multi-user systems is presented. Simulation results show that the proposed ZFBF scheme with receiver antenna selection （ZFBF-AS） achieves considerable throughput improvement over the ZFBF scheme with single receiver antenna. The results also show that, with multi-user diversity, the ZFBF-AS scheme approaches the throughput performance of the ZFBF scheme using all receiver antennas （ZFBF-WO-AS） when the base station adopts semi-orthogonal user selection （SUS） algorithm, and achieves larger throughput when the base station adopts the Round-robin scheduling algorithm. Compared with ZFBF-WO-AS, the proposed ZFBF-AS scheme can reduce the cost of user equipments and the channel state information requirement at the transmitter （CSIT） as well as the multiuser scheduling complexity at the transmitter.展开更多
基于显色体系和破壁条件的优化,构建了酶解破壁与显色反应相结合的氨基酸脱氢酶突变体高通量筛选方法。以颜色和吸光度表征内消旋-2,6-二氨基庚二酸脱氢酶(StDAPDH)酶活,以碘硝基四唑紫(INT)-吩嗪硫酸甲酯(PMS)为显色剂,通过其与StDAPD...基于显色体系和破壁条件的优化,构建了酶解破壁与显色反应相结合的氨基酸脱氢酶突变体高通量筛选方法。以颜色和吸光度表征内消旋-2,6-二氨基庚二酸脱氢酶(StDAPDH)酶活,以碘硝基四唑紫(INT)-吩嗪硫酸甲酯(PMS)为显色剂,通过其与StDAPDH的偶联反应优化了显色体系;以StDAPDH酶活为评价指标,在单因素实验的基础上,采用响应面法探究了菌体量、破壁时间、溶菌酶加量对菌体破壁效果的影响。确定最优显色体系为:INT浓度0.1 mg·mL^(-1)、PMS浓度0.5μg·mL^(-1)、检测波长510 nm;确定最优菌体破壁条件为:30 mL OD 600值为1.5的菌悬液,离心后用10 mL PBS缓冲液重悬菌体沉淀,加入0.2 mg·mL^(-1)的溶菌酶,在37℃下破壁50 min。该方法简单高效,为氨基酸脱氢酶突变体的高通量筛选提供了一定参考。展开更多
文章提出一种在片上系统(System on Chip,SoC)实现高吞吐率的有限状态熵编码(finite state entropy,FSE)算法。通过压缩率、速度、资源消耗、功耗4个方面对所提出的编码器和解码器与典型的硬件哈夫曼编码(Huffman coding,HC)进行性能比...文章提出一种在片上系统(System on Chip,SoC)实现高吞吐率的有限状态熵编码(finite state entropy,FSE)算法。通过压缩率、速度、资源消耗、功耗4个方面对所提出的编码器和解码器与典型的硬件哈夫曼编码(Huffman coding,HC)进行性能比较,结果表明,所提出的硬件FSE编码器和解码器具有显著优势。硬件FSE(hFSE)架构实现在SoC的处理系统和可编程逻辑块(programmable logic,PL)上,通过高级可扩展接口(Advanced eXtensible Interface 4,AXI4)总线连接SoC的处理系统和可编程逻辑块。算法测试显示,FSE算法在非均匀数据分布和大数据量情况下,具有更好的压缩率。该文设计的编码器和解码器已在可编程逻辑块上实现,其中包括1个可配置的缓冲模块,将比特流作为单字节或双字节配置输出到8 bit位宽4096深度或16 bit位宽2048深度的块随机访问存储器(block random access memory,BRAM)中。所提出的FSE硬件架构为实时压缩应用提供了高吞吐率、低功耗和低资源消耗的硬件实现。展开更多
基金supported by the National Natural Science Foundation of China (60496314)the National High Technology Research and Development Program of China (2006AA01Z266).
文摘A study on the zero-forcing beamforming （ZFBF） scheme with antenna selection at user terminals in downlink multi-antenna multi-user systems is presented. Simulation results show that the proposed ZFBF scheme with receiver antenna selection （ZFBF-AS） achieves considerable throughput improvement over the ZFBF scheme with single receiver antenna. The results also show that, with multi-user diversity, the ZFBF-AS scheme approaches the throughput performance of the ZFBF scheme using all receiver antennas （ZFBF-WO-AS） when the base station adopts semi-orthogonal user selection （SUS） algorithm, and achieves larger throughput when the base station adopts the Round-robin scheduling algorithm. Compared with ZFBF-WO-AS, the proposed ZFBF-AS scheme can reduce the cost of user equipments and the channel state information requirement at the transmitter （CSIT） as well as the multiuser scheduling complexity at the transmitter.
文摘基于显色体系和破壁条件的优化,构建了酶解破壁与显色反应相结合的氨基酸脱氢酶突变体高通量筛选方法。以颜色和吸光度表征内消旋-2,6-二氨基庚二酸脱氢酶(StDAPDH)酶活,以碘硝基四唑紫(INT)-吩嗪硫酸甲酯(PMS)为显色剂,通过其与StDAPDH的偶联反应优化了显色体系;以StDAPDH酶活为评价指标,在单因素实验的基础上,采用响应面法探究了菌体量、破壁时间、溶菌酶加量对菌体破壁效果的影响。确定最优显色体系为:INT浓度0.1 mg·mL^(-1)、PMS浓度0.5μg·mL^(-1)、检测波长510 nm;确定最优菌体破壁条件为:30 mL OD 600值为1.5的菌悬液,离心后用10 mL PBS缓冲液重悬菌体沉淀,加入0.2 mg·mL^(-1)的溶菌酶,在37℃下破壁50 min。该方法简单高效,为氨基酸脱氢酶突变体的高通量筛选提供了一定参考。
文摘文章提出一种在片上系统(System on Chip,SoC)实现高吞吐率的有限状态熵编码(finite state entropy,FSE)算法。通过压缩率、速度、资源消耗、功耗4个方面对所提出的编码器和解码器与典型的硬件哈夫曼编码(Huffman coding,HC)进行性能比较,结果表明,所提出的硬件FSE编码器和解码器具有显著优势。硬件FSE(hFSE)架构实现在SoC的处理系统和可编程逻辑块(programmable logic,PL)上,通过高级可扩展接口(Advanced eXtensible Interface 4,AXI4)总线连接SoC的处理系统和可编程逻辑块。算法测试显示,FSE算法在非均匀数据分布和大数据量情况下,具有更好的压缩率。该文设计的编码器和解码器已在可编程逻辑块上实现,其中包括1个可配置的缓冲模块,将比特流作为单字节或双字节配置输出到8 bit位宽4096深度或16 bit位宽2048深度的块随机访问存储器(block random access memory,BRAM)中。所提出的FSE硬件架构为实时压缩应用提供了高吞吐率、低功耗和低资源消耗的硬件实现。
