Developing parallel applications on heterogeneous processors is facing the challenges of 'memory wall',due to limited capacity of local storage,limited bandwidth and long latency for memory access. Aiming at t...Developing parallel applications on heterogeneous processors is facing the challenges of 'memory wall',due to limited capacity of local storage,limited bandwidth and long latency for memory access. Aiming at this problem,a parallelization approach was proposed with six memory optimization schemes for CG,four schemes of them aiming at all kinds of sparse matrix-vector multiplication (SPMV) operation. Conducted on IBM QS20,the parallelization approach can reach up to 21 and 133 times speedups with size A and B,respectively,compared with single power processor element. Finally,the conclusion is drawn that the peak bandwidth of memory access on Cell BE can be obtained in SPMV,simple computation is more efficient on heterogeneous processors and loop-unrolling can hide local storage access latency while executing scalar operation on SIMD cores.展开更多
为研究异构多核片上系统(multi-processor system on chip,MPSoC)在密集并行计算任务中的潜力,文章设计并实现了一种适用于粗粒度数据特征、面向任务级并行应用的异构多核系统动态调度协处理器,采用了片上缓存、任务输出的多级写回管理...为研究异构多核片上系统(multi-processor system on chip,MPSoC)在密集并行计算任务中的潜力,文章设计并实现了一种适用于粗粒度数据特征、面向任务级并行应用的异构多核系统动态调度协处理器,采用了片上缓存、任务输出的多级写回管理、任务自动映射、通讯任务乱序执行等机制。实验结果表明,该动态调度协处理器不仅能够实现任务级乱序执行等基本设计目标,还具有极低的调度开销,相较于基于动态记分牌算法的调度器,运行多个子孔径距离压缩算法的时间降低达17.13%。研究结果证明文章设计的动态调度协处理器能够有效优化目标场景下的任务调度效果。展开更多
5G,8K视频等新业务类型不断涌现,使得网络处理器(network processor,NP)的应用场景日趋复杂多样.为满足多样化网络应用在性能、灵活性以及服务质量保证等方面的差异化需求,传统NP试图在片上系统(system on chip,SoC)上集成大量处理器核...5G,8K视频等新业务类型不断涌现,使得网络处理器(network processor,NP)的应用场景日趋复杂多样.为满足多样化网络应用在性能、灵活性以及服务质量保证等方面的差异化需求,传统NP试图在片上系统(system on chip,SoC)上集成大量处理器核、高速缓存、加速器等异质处理资源,提供面向多样化应用场景的敏捷可定制能力.然而,随着摩尔定律和登纳德缩放定律失效问题的逐渐凸显,单片NP芯片研制在研发周期、成本、创新迭代等方面面临巨大挑战,越来越难以为继.针对上述问题,提出新型敏捷可定制NP架构ChipletNP,基于芯粒化(Chiplet)技术解耦异质资源,在充分利用成熟芯片产品及工艺的基础上,通过多个芯粒组合,满足不同应用场景下NP的快速定制和演化发展需求.基于ChipletNP设计实现了一款集成商用CPU、FPGA(field programmable gate array)和自研敏捷交换芯粒的银河衡芯敏捷NP芯片(YHHX-NP).基于该芯片的应用部署与实验结果表明,ChipletNP可支持NP的快速敏捷定制,能够有效承载SRv6(segment routing over IPv6)等新型网络协议与网络功能部署.其中,核心的敏捷交换芯粒相较于同级商用芯片能效比提升2倍以上,延迟控制在2.82μs以内,可以有效支持面向NP的Chiplet统一通信与集成.展开更多
基金Project(2008AA01A201) supported the National High-tech Research and Development Program of ChinaProjects(60833004, 60633050) supported by the National Natural Science Foundation of China
文摘Developing parallel applications on heterogeneous processors is facing the challenges of 'memory wall',due to limited capacity of local storage,limited bandwidth and long latency for memory access. Aiming at this problem,a parallelization approach was proposed with six memory optimization schemes for CG,four schemes of them aiming at all kinds of sparse matrix-vector multiplication (SPMV) operation. Conducted on IBM QS20,the parallelization approach can reach up to 21 and 133 times speedups with size A and B,respectively,compared with single power processor element. Finally,the conclusion is drawn that the peak bandwidth of memory access on Cell BE can be obtained in SPMV,simple computation is more efficient on heterogeneous processors and loop-unrolling can hide local storage access latency while executing scalar operation on SIMD cores.
文摘为研究异构多核片上系统(multi-processor system on chip,MPSoC)在密集并行计算任务中的潜力,文章设计并实现了一种适用于粗粒度数据特征、面向任务级并行应用的异构多核系统动态调度协处理器,采用了片上缓存、任务输出的多级写回管理、任务自动映射、通讯任务乱序执行等机制。实验结果表明,该动态调度协处理器不仅能够实现任务级乱序执行等基本设计目标,还具有极低的调度开销,相较于基于动态记分牌算法的调度器,运行多个子孔径距离压缩算法的时间降低达17.13%。研究结果证明文章设计的动态调度协处理器能够有效优化目标场景下的任务调度效果。
文摘5G,8K视频等新业务类型不断涌现,使得网络处理器(network processor,NP)的应用场景日趋复杂多样.为满足多样化网络应用在性能、灵活性以及服务质量保证等方面的差异化需求,传统NP试图在片上系统(system on chip,SoC)上集成大量处理器核、高速缓存、加速器等异质处理资源,提供面向多样化应用场景的敏捷可定制能力.然而,随着摩尔定律和登纳德缩放定律失效问题的逐渐凸显,单片NP芯片研制在研发周期、成本、创新迭代等方面面临巨大挑战,越来越难以为继.针对上述问题,提出新型敏捷可定制NP架构ChipletNP,基于芯粒化(Chiplet)技术解耦异质资源,在充分利用成熟芯片产品及工艺的基础上,通过多个芯粒组合,满足不同应用场景下NP的快速定制和演化发展需求.基于ChipletNP设计实现了一款集成商用CPU、FPGA(field programmable gate array)和自研敏捷交换芯粒的银河衡芯敏捷NP芯片(YHHX-NP).基于该芯片的应用部署与实验结果表明,ChipletNP可支持NP的快速敏捷定制,能够有效承载SRv6(segment routing over IPv6)等新型网络协议与网络功能部署.其中,核心的敏捷交换芯粒相较于同级商用芯片能效比提升2倍以上,延迟控制在2.82μs以内,可以有效支持面向NP的Chiplet统一通信与集成.
