在鳍型场效应晶体管(SOI FinFET)相关静电防护技术研究基础上,提出了一种新型的体区接触固定型绝缘体上硅鳍型场效应晶体管泄放钳位装置(Fix-base SOI FinFET Clamp)。该新型结构的器件解决了基区接触浮空在静电防护设计时引起的一系列...在鳍型场效应晶体管(SOI FinFET)相关静电防护技术研究基础上,提出了一种新型的体区接触固定型绝缘体上硅鳍型场效应晶体管泄放钳位装置(Fix-base SOI FinFET Clamp)。该新型结构的器件解决了基区接触浮空在静电防护设计时引起的一系列问题,而且对正常的FinFET工艺具有良好的兼容性。通过计算机辅助工艺设计(TCAD)仿真论证了Fix-base SOI FinFET Clamp具有明显效果,详细阐述和讨论了SOI FinFET和Fix-base SOI FinFET Clamp工作状态下的电流和热分布。展开更多
单粒子瞬态(SET)的电路仿真通常是注入双指数电流源来模拟,然而,纳米FinFET器件的SET采用单个双指数电流源模拟会带来较大误差。TCAD仿真结果较准确,但耗时较长,为了较为准确地电路仿真SET,提出了一种SET的复合双指数电流源模型。利用T...单粒子瞬态(SET)的电路仿真通常是注入双指数电流源来模拟,然而,纳米FinFET器件的SET采用单个双指数电流源模拟会带来较大误差。TCAD仿真结果较准确,但耗时较长,为了较为准确地电路仿真SET,提出了一种SET的复合双指数电流源模型。利用TCAD对电学特性校准的14 nm SOI FinFET器件的SET进行仿真,通过分析瞬态电流波形,对比双指数模型特点,提取特征参数,并利用遗传算法对模型参数进行优化处理,得到了关于线性能量转移(LET)的复合双电流源参数的解析模型。利用此复合双指数电流源模型与TCAD得到的瞬态电流波形、峰值和收集电荷量进行对比检验。结果显示,本文模型得到的SET电流波形与TCAD的基本吻合,与TCAD相比,模型的峰值电流的平均误差和最大误差分别为3.00%、5.06%;收集电荷量的平均误差和最大误差分别为4.02%、7.17%。展开更多
In this paper, we investigate the temperature and drain bias dependency of single event transient （SET） in 25-nm fin field-effect-transistor （FinFET） technology in a temperature range of 0-135 ℃ and supply voltag...In this paper, we investigate the temperature and drain bias dependency of single event transient （SET） in 25-nm fin field-effect-transistor （FinFET） technology in a temperature range of 0-135 ℃ and supply voltage range of 0.4 V- 1.6 V. Technology computer-aided design （TCAD） three-dimensional simulation results show that the drain current pulse duration increases from 0.6 ns to 3.4 ns when the temperature increases from 0 to 135 ℃. The charge collected increases from 45.5 ℃ to 436.9 fC and the voltage pulse width decreases from 0.54 ns to 0.18 ns when supply voltage increases from 0.4 V to 1.6 V. Furthermore, simulation results and the mechanism of temperature and bias dependency are discussed.展开更多
In this paper, we investigate the performance of the bulk fin field effect transistor （FinFET） through a three- dimensional （3D） full band Monte Carlo simulator with quantum correction. Several scattering mechanis...In this paper, we investigate the performance of the bulk fin field effect transistor （FinFET） through a three- dimensional （3D） full band Monte Carlo simulator with quantum correction. Several scattering mechanisms, such as the acoustic and optical phonon scattering, the ionized impurity scattering, the impact ionization scattering and the surface roughness scattering are considered in our simulator. The effects of the substrate bias and the surface roughness scattering near the Si/SiO2 interface on the performance of bulk FinFET are mainly discussed in our work. Our results show that the on-current of bulk FinFET is sensitive to the surface roughness and that we can reduce the substrate leakage current by modulating the substrate bias voltage.展开更多
Based on the BL09 terminal of China Spallation Neutron Source(CSNS),single event upset(SEU)cross sections of14 nm fin field-effect transistor(FinFET)and 65 nm quad data rate(QDR)static random-access memories(SRAMs)are...Based on the BL09 terminal of China Spallation Neutron Source(CSNS),single event upset(SEU)cross sections of14 nm fin field-effect transistor(FinFET)and 65 nm quad data rate(QDR)static random-access memories(SRAMs)are obtained under different incident directions of neutrons:front,back and side.It is found that,for both technology nodes,the“worst direction”corresponds to the case that neutrons traverse package and metallization before reaching the sensitive volume.The SEU cross section under the worst direction is 1.7-4.7 times higher than those under other incident directions.While for multiple-cell upset(MCU)sensitivity,side incidence is the worst direction,with the highest MCU ratio.The largest MCU for the 14 nm FinFET SRAM involves 8 bits.Monte-Carlo simulations are further performed to reveal the characteristics of neutron induced secondary ions and understand the inner mechanisms.展开更多
The conformal mapping of an electric field has been employed to develop an accurate parasitic capacitance model for nanoscale fin field-effect transistor（Fin FET） device. Firstly, the structure of the dual-layer spa...The conformal mapping of an electric field has been employed to develop an accurate parasitic capacitance model for nanoscale fin field-effect transistor（Fin FET） device. Firstly, the structure of the dual-layer spacers and the gate parasitic capacitors are thoroughly analyzed. Then, the Cartesian coordinate is transferred into the elliptic coordinate and the equivalent fringe capacitance model can be built-up by some arithmetical operations. In order to validate our proposed model, the comparison of statistical analysis between the proposed calculation and the 3D-TCAD simulation has been carried out, and several different material combinations of the dual-k structure have been considered. The results show that the proposed analytical model can accurately calculate the fringe capacitance of the Fin FET device with dual-k spacers.展开更多
文摘在鳍型场效应晶体管(SOI FinFET)相关静电防护技术研究基础上,提出了一种新型的体区接触固定型绝缘体上硅鳍型场效应晶体管泄放钳位装置(Fix-base SOI FinFET Clamp)。该新型结构的器件解决了基区接触浮空在静电防护设计时引起的一系列问题,而且对正常的FinFET工艺具有良好的兼容性。通过计算机辅助工艺设计(TCAD)仿真论证了Fix-base SOI FinFET Clamp具有明显效果,详细阐述和讨论了SOI FinFET和Fix-base SOI FinFET Clamp工作状态下的电流和热分布。
文摘单粒子瞬态(SET)的电路仿真通常是注入双指数电流源来模拟,然而,纳米FinFET器件的SET采用单个双指数电流源模拟会带来较大误差。TCAD仿真结果较准确,但耗时较长,为了较为准确地电路仿真SET,提出了一种SET的复合双指数电流源模型。利用TCAD对电学特性校准的14 nm SOI FinFET器件的SET进行仿真,通过分析瞬态电流波形,对比双指数模型特点,提取特征参数,并利用遗传算法对模型参数进行优化处理,得到了关于线性能量转移(LET)的复合双电流源参数的解析模型。利用此复合双指数电流源模型与TCAD得到的瞬态电流波形、峰值和收集电荷量进行对比检验。结果显示,本文模型得到的SET电流波形与TCAD的基本吻合,与TCAD相比,模型的峰值电流的平均误差和最大误差分别为3.00%、5.06%;收集电荷量的平均误差和最大误差分别为4.02%、7.17%。
基金Project supported by the State Key Program of the National Natural Science of China (Grant No. 60836004)the National Natural Science Foundation of China (Grant Nos. 61076025 and 60906014)
文摘In this paper, we investigate the temperature and drain bias dependency of single event transient （SET） in 25-nm fin field-effect-transistor （FinFET） technology in a temperature range of 0-135 ℃ and supply voltage range of 0.4 V- 1.6 V. Technology computer-aided design （TCAD） three-dimensional simulation results show that the drain current pulse duration increases from 0.6 ns to 3.4 ns when the temperature increases from 0 to 135 ℃. The charge collected increases from 45.5 ℃ to 436.9 fC and the voltage pulse width decreases from 0.54 ns to 0.18 ns when supply voltage increases from 0.4 V to 1.6 V. Furthermore, simulation results and the mechanism of temperature and bias dependency are discussed.
基金Project supported by the National Basic Research Program of China (Grant No. 2011CBA00604)
文摘In this paper, we investigate the performance of the bulk fin field effect transistor （FinFET） through a three- dimensional （3D） full band Monte Carlo simulator with quantum correction. Several scattering mechanisms, such as the acoustic and optical phonon scattering, the ionized impurity scattering, the impact ionization scattering and the surface roughness scattering are considered in our simulator. The effects of the substrate bias and the surface roughness scattering near the Si/SiO2 interface on the performance of bulk FinFET are mainly discussed in our work. Our results show that the on-current of bulk FinFET is sensitive to the surface roughness and that we can reduce the substrate leakage current by modulating the substrate bias voltage.
基金Project supported by the Key-Area Research and Development Program of Guangdong Province,China(Grant No.2019B010145001)the National Natural Science Foundation of China(Grant Nos.12075065 and 12175045)the Applied Fundamental Research Project of Guangzhou City,China(Grant No.202002030299)
文摘Based on the BL09 terminal of China Spallation Neutron Source(CSNS),single event upset(SEU)cross sections of14 nm fin field-effect transistor(FinFET)and 65 nm quad data rate(QDR)static random-access memories(SRAMs)are obtained under different incident directions of neutrons:front,back and side.It is found that,for both technology nodes,the“worst direction”corresponds to the case that neutrons traverse package and metallization before reaching the sensitive volume.The SEU cross section under the worst direction is 1.7-4.7 times higher than those under other incident directions.While for multiple-cell upset(MCU)sensitivity,side incidence is the worst direction,with the highest MCU ratio.The largest MCU for the 14 nm FinFET SRAM involves 8 bits.Monte-Carlo simulations are further performed to reveal the characteristics of neutron induced secondary ions and understand the inner mechanisms.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61574056 and 61204038)the Natural Science Foundation of Shanghai,China(Grant No.14ZR1412000)
文摘The conformal mapping of an electric field has been employed to develop an accurate parasitic capacitance model for nanoscale fin field-effect transistor（Fin FET） device. Firstly, the structure of the dual-layer spacers and the gate parasitic capacitors are thoroughly analyzed. Then, the Cartesian coordinate is transferred into the elliptic coordinate and the equivalent fringe capacitance model can be built-up by some arithmetical operations. In order to validate our proposed model, the comparison of statistical analysis between the proposed calculation and the 3D-TCAD simulation has been carried out, and several different material combinations of the dual-k structure have been considered. The results show that the proposed analytical model can accurately calculate the fringe capacitance of the Fin FET device with dual-k spacers.
