低密度奇偶校验(Low-Density Parity-Check,LDPC)码是第五代移动通信技术(5th Generation Mobile Communication Technology,5G)系统采用的信道编码技术之一,用于业务信道高速数据传输,具有很强的抗干扰能力和纠错能力。5G-LDPC码编译...低密度奇偶校验(Low-Density Parity-Check,LDPC)码是第五代移动通信技术(5th Generation Mobile Communication Technology,5G)系统采用的信道编码技术之一,用于业务信道高速数据传输,具有很强的抗干扰能力和纠错能力。5G-LDPC码编译码在嵌入式平台的实现是一个值得关注的研究方向。CEVA-XC4500数字信号处理(Digital Signal Processing,DSP)芯片具有极低功耗、高密度计算、集成了超长指令字(Very Long Instruction Word,VLIW)和单指令多数据(Single Instruction Multiple Data,SIMD)矢量功能的特点。针对CEVA-XC4500 DSP矢量汇编指令和内联指令集的特点,提出一系列针对5G-LDPC码编码的代码优化方法,使其满足5G-LDPC码编码工程应用指标要求。仿真结果表明,优化后的5G-LDPC码编码在CEVA-XC4500 DSP内核上表现良好,中长块编码吞吐率超过100 Mb/s、核心矩阵吞吐率超过1 Gb/s,最大吞吐率达到250 Mb/s、最大核心矩阵吞吐率达到1.6 Gb/s。如果CEVA-XC4500 DSP芯片的最大数据位宽将来能进一步增大,吞吐率可以做得更好。该5G-LDPC码编码的代码优化方法为其他信道编码在类似嵌入式平台的实现提供了参考。展开更多
With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and...With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and hence causes an increase in the raw bit error rate of data stored in the cells.Recently, low-density parity-check(LDPC)codes have appeared to be a promising solution to combat the interference of MLC NAND flash memory. However, the decoding complexity of the sum-product algorithm(SPA) is extremely high. In this paper, to improve the accuracy of the log likelihood ratio(LLR) information of each bit in each NAND flash memory cell, we adopt a non-uniform detection(N-UD) which uses the average maximum mutual information to determine the value of the soft-decision reference voltages.Furthermore, with an aim to reduce the decoding complexity and improve the decoding performance, we propose a modified soft reliabilitybased iterative majority-logic decoding(MSRBI-MLGD) algorithm, which uses a non-uniform quantizer based on power function to decode LDPC codes. Simulation results show that our design can offer a desirable trade-off between the performance and complexity for high-column-weight LDPC-coded MLC NAND flash memory.展开更多
基金supported in part by the NSF of China (61471131, 61771149, 61501126)NSF of Guangdong Province 2016A030310337+1 种基金the open research fund of National Mobile Communications Research Laboratory, Southeast University (No. 2018D02)the Guangdong Province Universities and Colleges Pearl River Scholar Funded Scheme (2017-ZJ022)
文摘With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and hence causes an increase in the raw bit error rate of data stored in the cells.Recently, low-density parity-check(LDPC)codes have appeared to be a promising solution to combat the interference of MLC NAND flash memory. However, the decoding complexity of the sum-product algorithm(SPA) is extremely high. In this paper, to improve the accuracy of the log likelihood ratio(LLR) information of each bit in each NAND flash memory cell, we adopt a non-uniform detection(N-UD) which uses the average maximum mutual information to determine the value of the soft-decision reference voltages.Furthermore, with an aim to reduce the decoding complexity and improve the decoding performance, we propose a modified soft reliabilitybased iterative majority-logic decoding(MSRBI-MLGD) algorithm, which uses a non-uniform quantizer based on power function to decode LDPC codes. Simulation results show that our design can offer a desirable trade-off between the performance and complexity for high-column-weight LDPC-coded MLC NAND flash memory.
