A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacr...A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.展开更多
A novel variable step-size modified super-exponential iteration(MSEI)decision feedback blind equalization(DFE)algorithm with second-order digital phase-locked loop is put forward to improve the convergence performance...A novel variable step-size modified super-exponential iteration(MSEI)decision feedback blind equalization(DFE)algorithm with second-order digital phase-locked loop is put forward to improve the convergence performance of super-exponential iteration DFE algorithm.Based on the MSEI-DFE algorithm,it is first proposed to develop an error function as an improvement to the error function of MSEI,which effectively achieves faster convergence speed of the algorithm.Subsequently,a hyperbolic tangent function variable step-size algorithm is developed considering the high variation rate of the hyperbolic tangent function around zero,so as to further improve the convergence speed of the algorithm.In the end,a second-order digital phase-locked loop is introduced into the decision feedback equalizer to track and compensate for the phase rotation of equalizer input signals.For the multipath underwater acoustic channel with mixed phase and phase rotation,quadrature phase shift keying(QPSK)and 16 quadrature amplitude modulation(16QAM)modulated signals are used in the computer simulation of the algorithm in terms of convergence and carrier recovery performance.The results show that the proposed algorithm can considerably improve convergence speed and steady-state error,make effective compensation for phase rotation,and efficiently facilitate carrier recovery.展开更多
软锁相环(Soft Phase-locked Loop,SPLL)在现代工业控制尤其是电网电压相位锁定中得到越来越多的应用。分析了SPLL的基本结构和工作原理,针对传统SPLL运算量大、不利于在数字处理器(Digital Signal Processor,DSP)上实现的缺点,设计了...软锁相环(Soft Phase-locked Loop,SPLL)在现代工业控制尤其是电网电压相位锁定中得到越来越多的应用。分析了SPLL的基本结构和工作原理,针对传统SPLL运算量大、不利于在数字处理器(Digital Signal Processor,DSP)上实现的缺点,设计了一种改进型电网电压SPLL。根据电网电压SPLL工作原理,结合坐标变换关系,从结果出发,通过相角已锁定的性质来做逆向思考简化控制算法。动态计算SPLL的PI参数,以使锁相功能动态响应更好、控制算法运算量更少。理论分析、仿真研究都表明改进后的SPLL算法简单,动态响应快,能够抑制电网电压三相不平衡及谐波干扰,能够应对电网突然掉电等故障,非常利于在DSP中实现。展开更多
文摘A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.
基金supported by the National Natural Science Foundation of China(61671461)。
文摘A novel variable step-size modified super-exponential iteration(MSEI)decision feedback blind equalization(DFE)algorithm with second-order digital phase-locked loop is put forward to improve the convergence performance of super-exponential iteration DFE algorithm.Based on the MSEI-DFE algorithm,it is first proposed to develop an error function as an improvement to the error function of MSEI,which effectively achieves faster convergence speed of the algorithm.Subsequently,a hyperbolic tangent function variable step-size algorithm is developed considering the high variation rate of the hyperbolic tangent function around zero,so as to further improve the convergence speed of the algorithm.In the end,a second-order digital phase-locked loop is introduced into the decision feedback equalizer to track and compensate for the phase rotation of equalizer input signals.For the multipath underwater acoustic channel with mixed phase and phase rotation,quadrature phase shift keying(QPSK)and 16 quadrature amplitude modulation(16QAM)modulated signals are used in the computer simulation of the algorithm in terms of convergence and carrier recovery performance.The results show that the proposed algorithm can considerably improve convergence speed and steady-state error,make effective compensation for phase rotation,and efficiently facilitate carrier recovery.
文摘软锁相环(Soft Phase-locked Loop,SPLL)在现代工业控制尤其是电网电压相位锁定中得到越来越多的应用。分析了SPLL的基本结构和工作原理,针对传统SPLL运算量大、不利于在数字处理器(Digital Signal Processor,DSP)上实现的缺点,设计了一种改进型电网电压SPLL。根据电网电压SPLL工作原理,结合坐标变换关系,从结果出发,通过相角已锁定的性质来做逆向思考简化控制算法。动态计算SPLL的PI参数,以使锁相功能动态响应更好、控制算法运算量更少。理论分析、仿真研究都表明改进后的SPLL算法简单,动态响应快,能够抑制电网电压三相不平衡及谐波干扰,能够应对电网突然掉电等故障,非常利于在DSP中实现。
