Based on the nullor equivalent model of the ideal op amp, the solvability of RLC op amp networks are discussed and some practical problems are analyzed. Then several necessary and sufficient topological conditions for...Based on the nullor equivalent model of the ideal op amp, the solvability of RLC op amp networks are discussed and some practical problems are analyzed. Then several necessary and sufficient topological conditions for unique solvability are given and their proofs are shown in detail.These conditions have great applications in the analysis, synthesis and diagnosis of networks. Finally the solvability of an illustrative network are analyzed as an example.展开更多
文摘Based on the nullor equivalent model of the ideal op amp, the solvability of RLC op amp networks are discussed and some practical problems are analyzed. Then several necessary and sufficient topological conditions for unique solvability are given and their proofs are shown in detail.These conditions have great applications in the analysis, synthesis and diagnosis of networks. Finally the solvability of an illustrative network are analyzed as an example.
文摘以TSMC0.18μmCMOS制程实现10位元(10-bit)、每秒取样2×107次、操作电压1.8 V的管线式(pipe-line)模拟数字转换器(ADC)芯片。本设计主要是使用1.5-bit/stage架构,并且配合运算放大器(op amp)共享(sharing)技术,拔除传统第一级取样保持放大器(SHA,sample and hold amplifier)以节省功耗。此芯片的量测结果为输入信号频率2 MHz时,输出的SNDR与ENOB各为46.2 dB与7.32-bit,包含焊线垫片(pad)的芯片面积为1.54(1.391×1.107)mm2,芯片功耗为29.2 mW。
