A 2.7-4.0 GHz dual-mode auto frequency calibration(AFC) fast locking PLL was designed for navigation system on chip(SoC). The SoC was composed of one radio frequency(RF) receiver, one baseband and several system contr...A 2.7-4.0 GHz dual-mode auto frequency calibration(AFC) fast locking PLL was designed for navigation system on chip(SoC). The SoC was composed of one radio frequency(RF) receiver, one baseband and several system control parts. In the proposed AFC block, both analog and digital modes were designed to complete the AFC process. In analog mode, the analog part sampled and detected the charge pump output tuning voltage, which would give the indicator to digital part to adjust the voltage control oscillator(VCO) capacitor bank. In digital mode, the digital part counted the phase lock loop(PLL) divided clock to judge whether VCO frequency was fast or slow. The analog and digital modes completed the auto frequency calibration function independently by internal switch. By designing a special switching algorithm, the switch of the digital and analog mode could be realized anytime during the lock and unlock detecting process for faster and more stable locking. This chip is fabricated in 0.13 μm RF complementary metal oxide semiconductor(CMOS) process, and the VCO supports the frequency range from 2.7 to 4.0 GHz. Tested 3.96 GHz frequency phase noise is -90 d Bc/Hz@100 k Hz frequency offset and -120 d Bc/Hz@1 MHz frequency offset. By using the analog mode in lock detection and digital mode in unlock detection, tested AFC time is less than 9 μs and the total PLL lock time is less than 19 μs. The SoC acquisition and tracking sensitivity are about-142 d Bm and-155 d Bm, respectively. The area of the proposed PLL is 0.35 mm^2 and the total SoC area is about 9.6 mm^2.展开更多
针对弱电网普遍存在的直流偏置、频率变化等问题,提出1种适合单相并网逆变器的改进反Park变换锁相环IPT-PLL(inverse Park transform phase-locked loop)技术。首先,在鉴相环节选用Park变换后的α分量为基准电压,解决电网电压直流偏置问...针对弱电网普遍存在的直流偏置、频率变化等问题,提出1种适合单相并网逆变器的改进反Park变换锁相环IPT-PLL(inverse Park transform phase-locked loop)技术。首先,在鉴相环节选用Park变换后的α分量为基准电压,解决电网电压直流偏置问题,采用1/4基波周期延时的方法构造其正交分量;其次,引入拉格朗日插值多项式逼近分数阶延时,以降低频率变化造成的延时计算误差,并理论分析PI调节器的设计方法;最后,通过实验验证了所提改进IPT-PLL频率适应性强,能明显抑制电网直流偏置干扰,且具有较好的动、静态性能。展开更多
针对常规基于二阶广义积分发生器的锁频环(second-order generalized integrator based frequency locked-loop,SOGI-FLL)在单相并网逆变器电压控制中对直流及谐波分量抑制能力不足,从而引起输出电压频率、相位振荡的问题,提出一种基于...针对常规基于二阶广义积分发生器的锁频环(second-order generalized integrator based frequency locked-loop,SOGI-FLL)在单相并网逆变器电压控制中对直流及谐波分量抑制能力不足,从而引起输出电压频率、相位振荡的问题,提出一种基于改进型SOGI-FLL的单相并网逆变器电压控制方法。该方法在常规SOGI-FLL控制的基础上,在电压信号输入端加入级联型谐振滤波环节来消除谐波分量;同时引入直流控制环节,借助输入电压误差估计值来消除直流分量,达到电网电压频率和相位快速跟踪效果,从而实现电压的自适应控制。使用MATLAB及RT-LAB硬件在环半实物平台,在频率突变、含直流分量及谐波分量的非理想电网环境中,对二阶广义积分器锁相环、双二阶广义积分器锁频环与改进型SOGI-FLL 3种控制方法进行仿真及实验。结果表明,所提改进型SOGI-FLL控制方法在消除直流及谐波干扰的同时,能在0.025 s内实现频率锁定,且频率偏差小于2%,可增强系统对非理想电网信号的适应能力,实现并网电压的快速跟踪,具有良好动态性能。展开更多
This paper presents an algorithm that aims to reduce the peak-to-average power ratio（PAPR） of orthogonal frequency division multiplexing（OFDM） communication systems while maintaining frequency tracking.The algorit...This paper presents an algorithm that aims to reduce the peak-to-average power ratio（PAPR） of orthogonal frequency division multiplexing（OFDM） communication systems while maintaining frequency tracking.The algorithm achieves PAPR reduction by applying the complex conjugates of the data symbol obtained from the frequency domain to cancel the phase of the data symbol.A likelihood estimator is used to obtain the sub-carrier phase error due to the residual carrier frequency offset（RCFO） using the same complex conjugates as a pilot signal.Furthermore,a joint time and frequency domain multicarrier phase locked loop（MPLL） is developed to compensate additional frequency offset.Simulation results show that this algorithm is capable of reducing PAPR without impacting the frequency tracking performance.展开更多
Global positioning system (GPS) for vehicle applications in the urban area is challenged by low signal intensity. The carrier loop based on fast Fourier transform (FFT) can obtain a high signal to noise ratio (SNR) ga...Global positioning system (GPS) for vehicle applications in the urban area is challenged by low signal intensity. The carrier loop based on fast Fourier transform (FFT) can obtain a high signal to noise ratio (SNR) gain by increasing the observation time. However, this leads to a major problem that the acceleration cannot be ignored. The performance of the FFT-based loop will decline with the acceleration increasing. This paper discusses the effect of the dynamic on FFT first. Then a high performance carrier tracking loop for weak GPS L5 signals is proposed. It combines discrete chirp-Fourier transform (DCFT) and the phase fitting method to estimate Doppler frequency and Doppler rate simultaneously. First, a sequence of integration results is used to perform DCFT to estimate coarse Doppler frequency and Doppler rate. Second, the phase of the sequence is calculated and used to perform linear fitting. By the phase fitting method, the fine Doppler frequency and Doppler rate can be estimated. The computation cost is small because the integration results are used and the phase fitting method needs only coarse estimates of Doppler frequency and Doppler rate. Compared with FFT and DCFT, the precision of the phase fitting method is not limited by the resolution. Thus the proposed loop can get high precision and low carrier to noise ratio (C/N-0) tracking threshold. Simulation results show this loop has a great improvement than conventional loops for urban weak-signal applications.展开更多
锁频环(frequency-locked loop,FLL)能够快速准确地获取电网的电压和频率信息,被广泛应用于电网同步。当前FLL参数调节在不同性能之间需折中处理,难以获得期望的动态响应。该文提出一种可采用标准化滤波器设计方法的锁频环技术。首先,...锁频环(frequency-locked loop,FLL)能够快速准确地获取电网的电压和频率信息,被广泛应用于电网同步。当前FLL参数调节在不同性能之间需折中处理,难以获得期望的动态响应。该文提出一种可采用标准化滤波器设计方法的锁频环技术。首先,利用小信号模型,设计能够解耦前置滤波器动态的频率观测环,从而使频率观测环内可独立设计滤波器,实现锁频环滤波的同时,灵活设计滤波参数。该方法能在简化计算量的同时提高滤波能力,并能观测频率变化率(rate of change of frequency,RoCoF)。最后,该文给出高阶低通滤波器(high-order low-pass filter,HOLPF)以及移动平均滤波器(moving average filter,MAF)两种设计方案,采用MATLAB/Simulink仿真及实验验证所提灵活动态FLL的有效性及正确性。展开更多
基金Project(2011912004)supported by the Major Program of the Economic & Information Commission Program of Guangdong Province,ChinaProjects(2011B010700065,2011A090200106)supported by the Major Program of the Department of Science and Technology of Guangdong Province,China
文摘A 2.7-4.0 GHz dual-mode auto frequency calibration(AFC) fast locking PLL was designed for navigation system on chip(SoC). The SoC was composed of one radio frequency(RF) receiver, one baseband and several system control parts. In the proposed AFC block, both analog and digital modes were designed to complete the AFC process. In analog mode, the analog part sampled and detected the charge pump output tuning voltage, which would give the indicator to digital part to adjust the voltage control oscillator(VCO) capacitor bank. In digital mode, the digital part counted the phase lock loop(PLL) divided clock to judge whether VCO frequency was fast or slow. The analog and digital modes completed the auto frequency calibration function independently by internal switch. By designing a special switching algorithm, the switch of the digital and analog mode could be realized anytime during the lock and unlock detecting process for faster and more stable locking. This chip is fabricated in 0.13 μm RF complementary metal oxide semiconductor(CMOS) process, and the VCO supports the frequency range from 2.7 to 4.0 GHz. Tested 3.96 GHz frequency phase noise is -90 d Bc/Hz@100 k Hz frequency offset and -120 d Bc/Hz@1 MHz frequency offset. By using the analog mode in lock detection and digital mode in unlock detection, tested AFC time is less than 9 μs and the total PLL lock time is less than 19 μs. The SoC acquisition and tracking sensitivity are about-142 d Bm and-155 d Bm, respectively. The area of the proposed PLL is 0.35 mm^2 and the total SoC area is about 9.6 mm^2.
文摘针对弱电网普遍存在的直流偏置、频率变化等问题,提出1种适合单相并网逆变器的改进反Park变换锁相环IPT-PLL(inverse Park transform phase-locked loop)技术。首先,在鉴相环节选用Park变换后的α分量为基准电压,解决电网电压直流偏置问题,采用1/4基波周期延时的方法构造其正交分量;其次,引入拉格朗日插值多项式逼近分数阶延时,以降低频率变化造成的延时计算误差,并理论分析PI调节器的设计方法;最后,通过实验验证了所提改进IPT-PLL频率适应性强,能明显抑制电网直流偏置干扰,且具有较好的动、静态性能。
文摘针对常规基于二阶广义积分发生器的锁频环(second-order generalized integrator based frequency locked-loop,SOGI-FLL)在单相并网逆变器电压控制中对直流及谐波分量抑制能力不足,从而引起输出电压频率、相位振荡的问题,提出一种基于改进型SOGI-FLL的单相并网逆变器电压控制方法。该方法在常规SOGI-FLL控制的基础上,在电压信号输入端加入级联型谐振滤波环节来消除谐波分量;同时引入直流控制环节,借助输入电压误差估计值来消除直流分量,达到电网电压频率和相位快速跟踪效果,从而实现电压的自适应控制。使用MATLAB及RT-LAB硬件在环半实物平台,在频率突变、含直流分量及谐波分量的非理想电网环境中,对二阶广义积分器锁相环、双二阶广义积分器锁频环与改进型SOGI-FLL 3种控制方法进行仿真及实验。结果表明,所提改进型SOGI-FLL控制方法在消除直流及谐波干扰的同时,能在0.025 s内实现频率锁定,且频率偏差小于2%,可增强系统对非理想电网信号的适应能力,实现并网电压的快速跟踪,具有良好动态性能。
基金supported by the National Natural Science Foundation of China(60872026)the Natural Science Foundation of Tianjin(09JCZDJC16900)
文摘This paper presents an algorithm that aims to reduce the peak-to-average power ratio（PAPR） of orthogonal frequency division multiplexing（OFDM） communication systems while maintaining frequency tracking.The algorithm achieves PAPR reduction by applying the complex conjugates of the data symbol obtained from the frequency domain to cancel the phase of the data symbol.A likelihood estimator is used to obtain the sub-carrier phase error due to the residual carrier frequency offset（RCFO） using the same complex conjugates as a pilot signal.Furthermore,a joint time and frequency domain multicarrier phase locked loop（MPLL） is developed to compensate additional frequency offset.Simulation results show that this algorithm is capable of reducing PAPR without impacting the frequency tracking performance.
基金supported by the National Natural Science Foundation of China(6140134061573059)the Areo Space T.T.&.C.Innovation Program(201515A)
文摘Global positioning system (GPS) for vehicle applications in the urban area is challenged by low signal intensity. The carrier loop based on fast Fourier transform (FFT) can obtain a high signal to noise ratio (SNR) gain by increasing the observation time. However, this leads to a major problem that the acceleration cannot be ignored. The performance of the FFT-based loop will decline with the acceleration increasing. This paper discusses the effect of the dynamic on FFT first. Then a high performance carrier tracking loop for weak GPS L5 signals is proposed. It combines discrete chirp-Fourier transform (DCFT) and the phase fitting method to estimate Doppler frequency and Doppler rate simultaneously. First, a sequence of integration results is used to perform DCFT to estimate coarse Doppler frequency and Doppler rate. Second, the phase of the sequence is calculated and used to perform linear fitting. By the phase fitting method, the fine Doppler frequency and Doppler rate can be estimated. The computation cost is small because the integration results are used and the phase fitting method needs only coarse estimates of Doppler frequency and Doppler rate. Compared with FFT and DCFT, the precision of the phase fitting method is not limited by the resolution. Thus the proposed loop can get high precision and low carrier to noise ratio (C/N-0) tracking threshold. Simulation results show this loop has a great improvement than conventional loops for urban weak-signal applications.
文摘锁频环(frequency-locked loop,FLL)能够快速准确地获取电网的电压和频率信息,被广泛应用于电网同步。当前FLL参数调节在不同性能之间需折中处理,难以获得期望的动态响应。该文提出一种可采用标准化滤波器设计方法的锁频环技术。首先,利用小信号模型,设计能够解耦前置滤波器动态的频率观测环,从而使频率观测环内可独立设计滤波器,实现锁频环滤波的同时,灵活设计滤波参数。该方法能在简化计算量的同时提高滤波能力,并能观测频率变化率(rate of change of frequency,RoCoF)。最后,该文给出高阶低通滤波器(high-order low-pass filter,HOLPF)以及移动平均滤波器(moving average filter,MAF)两种设计方案,采用MATLAB/Simulink仿真及实验验证所提灵活动态FLL的有效性及正确性。
