An error tolerant hardware efficient verylarge scale integration （VLSI） architecture for bitparallel systolic multiplication over dual base, which canbe pipelined, is presented. Since this architecture has thefeatur...An error tolerant hardware efficient verylarge scale integration （VLSI） architecture for bitparallel systolic multiplication over dual base, which canbe pipelined, is presented. Since this architecture has thefeatures of regularity, modularity and unidirectionaldata flow, this structure is well suited to VLSIimplementations. The length of the largest delay pathand area of this architecture are less compared to the bitparallel systolic multiplication architectures reportedearlier. The architecture is implemented using Austria Micro System＇s 0.35 μm CMOS （complementary metaloxide semiconductor） technology. This architecture canalso operate over both the dual-base and polynomialbase.展开更多
In high-speed railway(HSR)wireless communication,the rapid channel changes and limited high-capacity access cause significant impact on the link performance.Meanwhile,the Doppler shift caused by high mobility leads to...In high-speed railway(HSR)wireless communication,the rapid channel changes and limited high-capacity access cause significant impact on the link performance.Meanwhile,the Doppler shift caused by high mobility leads to the inter-carrier interference.In this paper,we propose a reconfigurable intelligent surface(RIS)-assisted receive spatial modulation(SM)scheme based on the spatial-temporal correlated HSR Rician channel.The characteristics of SM and the phase shift adjustment of RIS are used to mitigate the performance degradation in high mobility scenarios.Considering the influence of channel spatial-temporal correlation and Doppler shift,the effects of different parameters on average bit error rate(BER)performance and upper bound of ergodic capacity are analyzed.Therefore,a joint antenna and RIS-unit selection algorithm based on the antenna removal method is proposed to increase the capacity performance of communication links.Numerical results show that the proposed RIS-assisted receive SM scheme can maintain high transmission capacity compared to the conventional HSR-SM scheme,whereas the degradation of BER performance can be compensated by arranging a large number of RIS-units.In addition,selecting more RIS-units has better capacity performance than activating more antennas in the low signal-to-noise ratio regions.展开更多
文摘An error tolerant hardware efficient verylarge scale integration （VLSI） architecture for bitparallel systolic multiplication over dual base, which canbe pipelined, is presented. Since this architecture has thefeatures of regularity, modularity and unidirectionaldata flow, this structure is well suited to VLSIimplementations. The length of the largest delay pathand area of this architecture are less compared to the bitparallel systolic multiplication architectures reportedearlier. The architecture is implemented using Austria Micro System＇s 0.35 μm CMOS （complementary metaloxide semiconductor） technology. This architecture canalso operate over both the dual-base and polynomialbase.
基金supported in part by National Natural Science Foundation of China under Grant 62461024Jiangxi Provincial Natural Science Foundation of China under Grant 20224ACB202001.
文摘In high-speed railway(HSR)wireless communication,the rapid channel changes and limited high-capacity access cause significant impact on the link performance.Meanwhile,the Doppler shift caused by high mobility leads to the inter-carrier interference.In this paper,we propose a reconfigurable intelligent surface(RIS)-assisted receive spatial modulation(SM)scheme based on the spatial-temporal correlated HSR Rician channel.The characteristics of SM and the phase shift adjustment of RIS are used to mitigate the performance degradation in high mobility scenarios.Considering the influence of channel spatial-temporal correlation and Doppler shift,the effects of different parameters on average bit error rate(BER)performance and upper bound of ergodic capacity are analyzed.Therefore,a joint antenna and RIS-unit selection algorithm based on the antenna removal method is proposed to increase the capacity performance of communication links.Numerical results show that the proposed RIS-assisted receive SM scheme can maintain high transmission capacity compared to the conventional HSR-SM scheme,whereas the degradation of BER performance can be compensated by arranging a large number of RIS-units.In addition,selecting more RIS-units has better capacity performance than activating more antennas in the low signal-to-noise ratio regions.
