In this paper, a linear-to-circular polarization converter using a three-layer frequency selective surface based on Ishaped circular structure resonant is presented and investigated. Numerical simulations exhibit that...In this paper, a linear-to-circular polarization converter using a three-layer frequency selective surface based on Ishaped circular structure resonant is presented and investigated. Numerical simulations exhibit that when the normal ypolarized waves impinge on this device propagating towards ＋z direction, the two orthogonal components of the transmitted waves have a 90° phase difference as well as the nearly equal amplitudes at the resonant frequency of 7.04 GHz, which means that the left-hand circular polarization is realized in transmission. For validating the proposed design, a prototype which consists of 25 × 25 elements has been designed, manufactured and measured. The measured results are in good agreement with the simulated ones, showing that the polarization conversion transmission is over-3 dB in the frequency range of 5.22–8.08 GHz and the axial ratio is below 3 dB from 5.86 GHz to 7.34 GHz.展开更多
Forhigh power applications,multilevel converters have many advantages in comparison with other circuit topologies with output transformers. Cascaded inverters are one type of multilevel converters,they are easy to imp...Forhigh power applications,multilevel converters have many advantages in comparison with other circuit topologies with output transformers. Cascaded inverters are one type of multilevel converters,they are easy to implement,very suitable for modularized layout and packaging.Their manufacturing cost is low.A multilevel PWM technique,called as General Technique of Selected Harmonics Elimination (GTSHE) ,is proposed in the paper. A general harmonic elimination equation for N cells,M pulses per half cycle,nth harmonic is derived,and verified by simulation results.展开更多
In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LA...In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.展开更多
Large number of antennas and higher bandwidth usage in massive multiple-input-multipleoutput(MIMO)systems create immense burden on receiver in terms of higher power consumption.The power consumption at the receiver ra...Large number of antennas and higher bandwidth usage in massive multiple-input-multipleoutput(MIMO)systems create immense burden on receiver in terms of higher power consumption.The power consumption at the receiver radio frequency(RF)circuits can be significantly reduced by the application of analog-to-digital converter(ADC)of low resolution.In this paper we investigate bandwidth efficiency(BE)of massive MIMO with perfect channel state information(CSI)by applying low resolution ADCs with Rician fadings.We start our analysis by deriving the additive quantization noise model,which helps to understand the effects of ADC resolution on BE by keeping the power constraint at the receiver in radar.We also investigate deeply the effects of using higher bit rates and the number of BS antennas on bandwidth efficiency(BE)of the system.We emphasize that good bandwidth efficiency can be achieved by even using low resolution ADC by using regularized zero-forcing(RZF)combining algorithm.We also provide a generic analysis of energy efficiency(EE)with different options of bits by calculating the energy efficiencies(EE)using the achievable rates.We emphasize that satisfactory BE can be achieved by even using low-resolution ADC/DAC in massive MIMO.展开更多
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61471387,61271250,and 61571460)
文摘In this paper, a linear-to-circular polarization converter using a three-layer frequency selective surface based on Ishaped circular structure resonant is presented and investigated. Numerical simulations exhibit that when the normal ypolarized waves impinge on this device propagating towards ＋z direction, the two orthogonal components of the transmitted waves have a 90° phase difference as well as the nearly equal amplitudes at the resonant frequency of 7.04 GHz, which means that the left-hand circular polarization is realized in transmission. For validating the proposed design, a prototype which consists of 25 × 25 elements has been designed, manufactured and measured. The measured results are in good agreement with the simulated ones, showing that the polarization conversion transmission is over-3 dB in the frequency range of 5.22–8.08 GHz and the axial ratio is below 3 dB from 5.86 GHz to 7.34 GHz.
文摘Forhigh power applications,multilevel converters have many advantages in comparison with other circuit topologies with output transformers. Cascaded inverters are one type of multilevel converters,they are easy to implement,very suitable for modularized layout and packaging.Their manufacturing cost is low.A multilevel PWM technique,called as General Technique of Selected Harmonics Elimination (GTSHE) ,is proposed in the paper. A general harmonic elimination equation for N cells,M pulses per half cycle,nth harmonic is derived,and verified by simulation results.
基金Supported by National Natural Science Foundation of China (No. 10405023)Knowledge Innovation Program of The Chinese Academy of Sciences (KJCX2-YW-N27)
文摘In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.
文摘Large number of antennas and higher bandwidth usage in massive multiple-input-multipleoutput(MIMO)systems create immense burden on receiver in terms of higher power consumption.The power consumption at the receiver radio frequency(RF)circuits can be significantly reduced by the application of analog-to-digital converter(ADC)of low resolution.In this paper we investigate bandwidth efficiency(BE)of massive MIMO with perfect channel state information(CSI)by applying low resolution ADCs with Rician fadings.We start our analysis by deriving the additive quantization noise model,which helps to understand the effects of ADC resolution on BE by keeping the power constraint at the receiver in radar.We also investigate deeply the effects of using higher bit rates and the number of BS antennas on bandwidth efficiency(BE)of the system.We emphasize that good bandwidth efficiency can be achieved by even using low resolution ADC by using regularized zero-forcing(RZF)combining algorithm.We also provide a generic analysis of energy efficiency(EE)with different options of bits by calculating the energy efficiencies(EE)using the achievable rates.We emphasize that satisfactory BE can be achieved by even using low-resolution ADC/DAC in massive MIMO.
