A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacr...A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.展开更多
针对弱电网普遍存在的直流偏置、频率变化等问题,提出1种适合单相并网逆变器的改进反Park变换锁相环IPT-PLL(inverse Park transform phase-locked loop)技术。首先,在鉴相环节选用Park变换后的α分量为基准电压,解决电网电压直流偏置问...针对弱电网普遍存在的直流偏置、频率变化等问题,提出1种适合单相并网逆变器的改进反Park变换锁相环IPT-PLL(inverse Park transform phase-locked loop)技术。首先,在鉴相环节选用Park变换后的α分量为基准电压,解决电网电压直流偏置问题,采用1/4基波周期延时的方法构造其正交分量;其次,引入拉格朗日插值多项式逼近分数阶延时,以降低频率变化造成的延时计算误差,并理论分析PI调节器的设计方法;最后,通过实验验证了所提改进IPT-PLL频率适应性强,能明显抑制电网直流偏置干扰,且具有较好的动、静态性能。展开更多
锁频环(frequency-locked loop,FLL)能够快速准确地获取电网的电压和频率信息,被广泛应用于电网同步。当前FLL参数调节在不同性能之间需折中处理,难以获得期望的动态响应。该文提出一种可采用标准化滤波器设计方法的锁频环技术。首先,...锁频环(frequency-locked loop,FLL)能够快速准确地获取电网的电压和频率信息,被广泛应用于电网同步。当前FLL参数调节在不同性能之间需折中处理,难以获得期望的动态响应。该文提出一种可采用标准化滤波器设计方法的锁频环技术。首先,利用小信号模型,设计能够解耦前置滤波器动态的频率观测环,从而使频率观测环内可独立设计滤波器,实现锁频环滤波的同时,灵活设计滤波参数。该方法能在简化计算量的同时提高滤波能力,并能观测频率变化率(rate of change of frequency,RoCoF)。最后,该文给出高阶低通滤波器(high-order low-pass filter,HOLPF)以及移动平均滤波器(moving average filter,MAF)两种设计方案,采用MATLAB/Simulink仿真及实验验证所提灵活动态FLL的有效性及正确性。展开更多
文摘A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.
文摘针对弱电网普遍存在的直流偏置、频率变化等问题,提出1种适合单相并网逆变器的改进反Park变换锁相环IPT-PLL(inverse Park transform phase-locked loop)技术。首先,在鉴相环节选用Park变换后的α分量为基准电压,解决电网电压直流偏置问题,采用1/4基波周期延时的方法构造其正交分量;其次,引入拉格朗日插值多项式逼近分数阶延时,以降低频率变化造成的延时计算误差,并理论分析PI调节器的设计方法;最后,通过实验验证了所提改进IPT-PLL频率适应性强,能明显抑制电网直流偏置干扰,且具有较好的动、静态性能。
文摘锁频环(frequency-locked loop,FLL)能够快速准确地获取电网的电压和频率信息,被广泛应用于电网同步。当前FLL参数调节在不同性能之间需折中处理,难以获得期望的动态响应。该文提出一种可采用标准化滤波器设计方法的锁频环技术。首先,利用小信号模型,设计能够解耦前置滤波器动态的频率观测环,从而使频率观测环内可独立设计滤波器,实现锁频环滤波的同时,灵活设计滤波参数。该方法能在简化计算量的同时提高滤波能力,并能观测频率变化率(rate of change of frequency,RoCoF)。最后,该文给出高阶低通滤波器(high-order low-pass filter,HOLPF)以及移动平均滤波器(moving average filter,MAF)两种设计方案,采用MATLAB/Simulink仿真及实验验证所提灵活动态FLL的有效性及正确性。
