摘要
本文提出一种能够明显减小正码速调整等候抖动的新方法——分离塞入比法。采用此方法的超大规模专用集成电路已在日本制成。本文简介这种方法提出的背景、原理、实验结果及应用特点。
This paper presents a new method which can be used to obiviously reduce the waiting jitter in positive justification by means of splitting stuff ratio of positive justification. The VLSI designed for this method has been made in Japan.This paper describes the principle of this method and the experiment results. Finally, the application of this method will be briefly introduced.
出处
《通信学报》
EI
CSCD
北大核心
1992年第1期45-51,共7页
Journal on Communications
