摘要
针对高速长线数据传输中可靠性低的问题,提出了一种均衡可靠性和高速传输的设计.设计中以LVDS作为传输高速接口,FPGA作为逻辑控制芯片,在硬件电路上加入均衡电路和软件程序上采用正反差错编码方式两方面提高传输可靠性.对总体设计方案和各电路模块进行了详细介绍和分析,以及对程序的实现进行了描述.最后给出了设计的试验结果,验证了本设计的传输可靠性.
Aiming at the problem of low reliability in high speed data transmission over a long distance,this paper proposes a design that balanced reliability and high-speed transmission.The design is used LVDS as the high-speed transmission interfaces,FPGA as the logic control chip,the hardware circuit joined the equalization circuit and software program used positive and inverse codes as error control coding improve transmission reliability.The overall design scheme and the circuit module has carried on the detailed introduction and analysis,and has described the implementation of the program.Finally presents the design of the test results,also verify the transmission reliability of the design.
出处
《微电子学与计算机》
CSCD
北大核心
2014年第9期131-134,共4页
Microelectronics & Computer
基金
国家自然科学基金项目(61004127)
