摘要
讨论了RTL级VHDL顺序语句的语法、语义规则 ,以及功能元件、存储元件、通路元件的VHDL顺序语句的造型 ;并以if,case和赋值语句为核心 ,详细说明了if,case和赋值语句的语句结构树的生成算法 ,以及基于该语句结构树的VHDL顺序语句格式判别。
The paper discusses the standard of syntax and semantics of VHDL sequential statements in the register transfer level (RTL) synthesizable design along with templates of logic function, storage, and gateway components in these statements. The author presents the algorithm of building construction tree of if, case and Assignment statements. The algorithm of format discriminance, component partition and generation of circuit structure, based on the statement construction tree are demonstrated.
出处
《计算机辅助设计与图形学学报》
EI
CSCD
北大核心
2003年第9期1112-1117,共6页
Journal of Computer-Aided Design & Computer Graphics
基金
上海市教委基金 ( 0 1A0 5 )资助
