摘要
本文提出了一种可编程复接方法和结构 ,通过对编程端的设置可得到 2∶1、3∶1、4∶1及 5∶1的复接模式 .该方法鲁棒性强、应用范围广 ,其组合可实现除包含大于 6的质数之外所有路数的复接 ,解决了光纤通信系统中不同复接模式对应不同复接结构的问题 .通过理论推导 ,本文着重分析了器件延时和时钟相位对芯片工作的影响 ,并指出了解决途径 .基于本方法和结构的全定制单片集成电路采用 0 35 μmCMOS工艺制造 ,芯片面积为 2 4 19mm2 ,实现了串行输出最高数据速率为 1 6 2Gbps的 10∶1复接 .在 1 2 5Gbps标准速率 ,工作电压 3 3V ,负载为 5 0Ω的条件下 ,功耗仅为174 84mW ,输出电压峰 峰值可达到 2 4 2V ,占空比为 4 9% ,抖动为 35psrms.测试结果表明芯片在复接性能、速度、功耗和面积优化方面的先进性 ,可满足不同吉比特率通信系统的要求 。
A robust configurable multiplexing approach is proposed, which presented 2:1,3:1,4:1,5:1 multiplex modes. Its cascade structure can realize all multiplexing modes except prime numbers of greater than 6. Based on this approach, an IC was designed to achieve the 10:1 multiplexing at the bit rate of 1.25 Gbps. It used high speed units to improve the design efficiency and to realize low power. It has been developed using 0.35 μm CMOS technology and the layout was finished in full custom method. The chip was realized through a foundry technology and measured on wafer. The chip area is 24.19 mm2. The power dissipation is 174.84 mW under a 3.3 V supply. The measured output voltage is 2.42 VP-P based on 50 Ω load, the duty cycle is 49% and the phase jitter is 35 ps rms at the 1.25 Gbps standard bit rate. The highest speed of serial data is 1.62 Gbps.
出处
《电子学报》
EI
CAS
CSCD
北大核心
2003年第8期1197-1200,共4页
Acta Electronica Sinica
基金
国家 8 63高技术计划 (No.2 0 0 1AA1 2 1 0 74)
国家杰出青年科学基金 (No.6982 51 0 1 )
