摘要
介绍了一种分频系数为整数和半整数的可控分频器的设计方法 ,利用Verilog HDL编程 ,在XilinxFoundation平台下实现分频器的综合和仿真 ,并用S0 5XL芯片实现。
This paper presents a method for designing a controllable frequency divider which division ratio is integer or half-integer. The frequency divider implemented with a S05XL chip is described in Veriliog-HDL, and synthesized, simulated with Xilinx foundation.
出处
《电子工程师》
2003年第6期44-46,共3页
Electronic Engineer
