摘要
研究计算机浮点运算的体系结构和浮点运算的逻辑加速问题.本文就浮点加速逻辑提出双向并行移位链式结构,并给出了该结构的逻辑实现方法.以此结构结合并行功能/数据浮点协处理器,可使计算机系统的浮点运算速度有数量级的提高.同时,还对该组成系统的 RISC模块结构进行了分析。
The system structure of floating-point arithmetic and the floating-point accelerating logic(FPA)are studied.It is put forward in the paper that a new structure is called floating-point accelerating logic with two-way parallel shift chain(TPSC).By the logic combined with the parallel function/data floating-point coprocessor,the rate of floating-point arithmetic in the computer system can be risen enormously.Sametime,the paper demon- strates the RISC construction of the floating-point arithmetic logic system.
出处
《电子科技大学学报》
EI
CAS
CSCD
北大核心
1992年第1期59-63,共5页
Journal of University of Electronic Science and Technology of China
基金
国家"七五"重点科技攻关基金.
关键词
浮点数
体系结构
并行移位链
floating-point data
system structure
parallel shift chain
floating-point accelerator
floating-point coprocessor
