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基于RISC-V架构的以太网IP设计及验证

Design and verification of ethernet IP core based on
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摘要 RISC-V作为一套开放式标准指令集架构,具有开源、指令精简、模块化、可扩展等优点,已成为越来越多SOC芯片的主流架构。以太网IP主要负责网络通信,是每个SOC芯片必不可少的模块。以太网IP为RISC-V生态系统提供了强大的网络通信能力,适用于从嵌入式设备到高性能计算的多种场景。采用开源的RISC-V+以太网IP的解决方案,替代ARM+以太网IP的传统方案,可以满足日益增长的国产化芯片需求,可以应用到国产化设备中,具有一定的应用价值。本文首先阐述了RISC-V架构SOC的功能结构,然后介绍了该架构中以太网IP的设计思路,包括该IP的功能模块设计、仿真验证、FPGA平台原型验证,并使用主流Iperf软件进行压力测试。 RISC-V,as an open standard instruction set architecture,has become the mainstream architecture for more and more SOC chip designs due to its advantages of open source,instruction simplifi⁃cation,modularity,and scalability.Ethernet IP is mainly responsible for network communication and is an essential module for every SOC chip.Ethernet IP provides powerful network communication capabilities for the RISC-V ecosystem,suitable for various scenarios ranging from embedded devices to high-performance computing.The open source RISC-V Ethernet IP solution can replace the traditional solution of ARM Ether⁃net IP to meet the growing demand for localized chips,and can be applied to localized weapon models,which has certain application value.This article first elaborates on the functional structure of the RISC-V architecture SOC,and then introduces the design ideas of the Ethernet IP in this architecture,including the functional module design,simulation verification,FPGA platform prototype verification,and stress test⁃ing using mainstream Iperf software.
作者 聂丹凤 马庆岩 NIE Danfeng;MA Qingyan(Department,The 47th Institute of China Electronics Technology Group Corporation,Shenyang 110000,China;PLA Unit 31411,Shenyang 110000,China)
出处 《微处理机》 2025年第4期35-40,共6页 Microprocessors
关键词 RISC-V 以太网 Iperf RISC-V Ethernet Iperf
作者简介 聂丹凤(1983-),女,辽宁省沈阳市人,硕士,高级工程师,主研方向:集成电路。
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