摘要
设计了一款基于超低通滤波器技术的低输出噪声的低压差线性稳压器(LDO)。根据典型LDO输出噪声的主要贡献点,采用含受控运放的超低通滤波器来降低基准信号的噪声,并解决低通滤波器截止频率与响应速度的矛盾。基于0.25μm CMOS工艺完成了LDO的设计和流片,其核心芯片的面积为700μm×750μm。测试结果表明,在输入电压为5 V、输出电压为3.3 V、负载电流为200 mA时,LDO的启动时间约为150μs,在1 kHz处的噪声为-138.15 dBV/√Hz,10 Hz~100 kHz内均方根(RMS)积分噪声约为17.0μV。
A low dropout linear regulator(LDO)with low output noise was designed based on ultra-low pass filter technology.According to the main contribution point of typical LDO output noise,an ultra-low pass filter controlled by operational amplifier was adopted in the design to reduce the noise of the reference signal,and solve the contradiction between the cutoff frequency and response speed of the low-pass filter.Based on 0.25μm CMOS process,the LDO with a core chip area of 700μmx750μm was designed and fabricated.The test results show that the startup time of the LDO is about 150μs at a load current of 200 mA,when the input voltage is 5 V and the output voltage is 3.3 V.The noise is-138.15 dBV/√Hz,10 Hz~100 kHz,and the root-mean-square(RMS)integrated noise is about 17.0μV in the range of 10 Hz-100 kHz.
作者
李飞宇
陈君涛
周爵
朱安康
Li Feiyu;Chen Juntao;Zhou Jue;Zhu Ankang(SUNV Electronics Technology Co.,Lid.,Suzhou 215000,China)
出处
《半导体技术》
北大核心
2025年第3期282-288,共7页
Semiconductor Technology
作者简介
李飞宇(1992-),男,重庆人,硕士,工程师,主要从事电源管理集成电路设计研究工作。
