摘要
晶圆级键合是实现多层硅基模块内部互连的关键工艺,针对硅片在晶圆级键合工艺中的开裂现象,建立了硅基刻蚀腔体在键合工艺中的力学模型,经样件实验验证,该模型可以准确预估腔体的开裂现象。在此基础上设计了硅片键合实验,通过引入硅通孔(TSV)的应力集中因子确定了硅基晶圆级键合的应力失效判据。而后通过参数化仿真系统性探究了硅基刻蚀腔体面积及腔体形状等因素对键合应力的影响规律,并绘制出刻蚀腔体设计可靠范围图。结果表明,硅片键合可靠腔体临界面积约为21 mm^(2),且腔体形状越接近正方形越易开裂。该研究为多层硅基模块刻蚀腔体的可靠性设计提供了参考。
Wafer-level bonding is a key process for realizing the internal interconnection of multilayer silicon-based modules.In view of the cracking phenomenon of the silicon wafer during the wafer-level bonding process,the mechanical model of silicon-based etching cavity during bonding process was estab-lished,and the model can accurately predict the cracking phenomenon of the cavity as verified by the sample test.On this basis,the silicon wafer bonding test was designed,and the stress failure criterion for the silicon-based wafer-level bonding was determined by introducing the stress concentration factor of through silicon via(TSV).And then the influence law of the area and shape of the silicon-based etching cavity and other factors on the bonding stress was systematically explored by parametric simulation,and the reliable range diagram of the etching cavity design was drawn.The results show that the critical area of the reliable cavity for silicon wafer bonding is about 21 mm',and the closer the cavity shape is to square,the more likely the crack failure occurs.This study provides reference for the reliability design of multilayer silicon-based module etching cavity.
作者
马将
郜佳佳
杨栋
Ma Jiang;Gao Jiajia;Yang Dong(The 13^(th)Research Institute,CETC,Shijiazhuang 050051,China)
出处
《半导体技术》
CAS
北大核心
2024年第7期674-681,共8页
Semiconductor Technology
关键词
晶圆级键合
多层硅基模块
刻蚀腔体
硅通孔(TSV)
可靠性
wafer-level bonding
multilayer silicon-based module
etching cavity
through silicon via(TSV)
reliability
作者简介
马将(1981-),男,山东潍坊人,工作重点涉及半导体器件与技术、半导体情报研究等。
