摘要
为实现数字通信对高速模数转换器的要求,基于0.18μm SiGe BiCMOS工艺提出了一款8 GS/s采样率、6 bit的采样保持电路。电路采用全差分开环结构,利用射极跟随型采样开关实现了电路高采样率。采样开关中采用晶体管线性补偿技术,有效地提高了采样保持电路的线性度。输出缓冲电路采用级联结构实现高线性度,并提高了电路的驱动能力。测试结果发现,在采样模式下单端输入信号频率4 GHz、采样时钟频率8 GHz条件下,有效位数为5.4 bit,无杂散动态范围为37.6 dB,总谐波失真为37.5 dB,总功耗为450 mW,芯片尺寸为0.68 mm×0.68 mm。
In order to realize the requirements of digital communication for high⁃speed analog⁃to⁃digital converters,a 6 bit sample and hold circuit with an 8 GS/s sampling rate was proposed based on the 0.18μm SiGe BiCMOS technology.The circuit adopted a fully differential open⁃loop structure,and a high sampling rate of the circuit was achieved by using an emitter follower sampling switch.The transistor linear compensation technology was used in the sampling switch,which effectively improved the linearity of the sample and hold circuit.The output buffer circuit adopted a cascade structure to achieve high linearity and improved the driving capability of the circuit.The test results show that under the conditions of a single⁃ended input signal frequency of 4 GHz in the sampling mode and a sampling clock frequency of 8 GHz,the effective number of bits is 5.4 bit,the spurious⁃free dynamic range is 37.6 dB,the total harmonic distortion is 37.5 dB,the total power consumption is 450 mW and the chip size is 0.68 mm×0.68 mm.
作者
李飞
吴洪江
龚剑
曹慧斌
Li Fei;Wu Hongjiang;Gong Jian;Cao Huibin(The 13th Research Institute,CETC,Shijiazhuang 050051,China)
出处
《半导体技术》
CAS
北大核心
2024年第5期499-504,共6页
Semiconductor Technology
作者简介
李飞(1998—),男,河北沧州人,硕士研究生,研究方向为数模混合集成电路设计;通信作者:吴洪江(1964—),男,河北衡水人,博士,研究员,主要研究方向为微波集成电路设计和固态微波器件研制。
