摘要
面向RISC-V处理器五级流水线数据通路,设计了基于FPGA的RISC-V指令集子集RV32I的指令译码电路。电路分为主译码电路和程序计数器输入选择(PCSel)译码电路,使用Verilog HDL编程设计,并进行了系列优化:使用时序约束工具分析时序状态,设定约束后对电路进行综合,降低电路延迟;利用无关项化简组合逻辑,减少模块输入输出项,减少电路级联;构建独立的32位串并行数值比较器;插入流水线,提高电路工作频率。电路基于FPGA芯片CycloneⅣEP4CE6F17C6进行设计,使用Quartus Prime 17.1对电路进行仿真,仿真结果表明:在Slow 1200 m V 85℃条件下,指令译码电路达到295.6 MHz的工作频率,相比同类设计具有高速和低资源消耗的特点。
An instruction decoding circuit for the subset of RV32I of RISC-V instruction set is designd based on FPGA.The circuit is composed of a main decoding circuit and a program counter input selection decoding circuit,which is designed by using Verilog.A series of optimizations have been made;the timing sequence being analyzed with the timing sequence constraint tool,and the circuit being synthe-sized after the constraints are set to reduce delay;making full use of irrelevant items to simplify combinational logic,and reducing mod-ule input and output items to reduce circuit cascade;building an independent 32-bit serial-parallel numeric comparator as the core of branch comparator to improve the speed of circuit;pluging pipeline to increase the frequency.The circuit is designed based on the FPGA chip of Cyclone IV EP4CE6F17C6 and simulated with Quartus Prime 17.1.The simulation results show that under the condition of Slow 1200 mV 85℃,the circuit can work at 295.6 MHz.Compared with similar design,it has the advantages of high speed and low resource usage.
作者
陈勇
毛宇鹏
朱玉全
黄盛杰
陈宇宸
CHEN Yong;MAO Yupeng;ZHU Yuquan;HUANG Shengjie;CHEN Yuchen(School of Computer Science and Communication Engineering,Jiangsu University,Zhenjiang Jiangsu 212013,China;Jiangsu Longrui Internet of Things Technology Co.,Ltd.,Nanjing Jiangsu 211106,China;Jiangsu Agricultural Machinery Test and Appraisal Station,Nanjing Jiangsu 210017,China;Nanjing Tech University,Nanjing Jiangsu 211816,China)
出处
《电子器件》
CAS
北大核心
2023年第2期297-302,共6页
Chinese Journal of Electron Devices
作者简介
陈勇(1977-),硕士,正高级工程师,主要研究方向为物联网、计算机与通信技术,长期致力于农业物联网、工业大数据等领域的应用技术研究和产业链建设。
