摘要
提出了一种宽带低相噪频率合成器的设计方法.采用了数字锁相技术,该锁相技术主要由锁相环(phase locked loop,PLL)芯片、有源环路滤波器、宽带压控振荡器和外置宽带分频器等构成,实现了10～20GHz范围内任意频率输出,具有输出频率宽、相位噪声低、集成度高、功耗低和成本低等优点.最后对该PLL电路杂散抑制和相位噪声的指标进行了测试,测试结果表明该PLL输出10GHz时相位噪声优于-109dBc/Hz@1kHz,该指标与直接式频率合成器实现的指标相当.
A design method of wideband low phase noise frequency synthesizer is proposed in the paper.Digital phase locked loop(PLL)technology is adopted.The frequency synthesizer is mainly composed of PLL chip,active loop filter,wideband voltage controlled oscillator(VCO)and external wideband divider.The PLL can realize any frequency output in 10-20 GHz.And it has the advantages of wide output frequency,low phase noise,high integration,low power consumption and low cost.The phase noise test curves are presented,and the experimental results show that the phase noise of the PLL is better than that of-109 dBc/Hz@1 kHz when the output is 10 GHz,which is very close to the phase noise of the direct frequency synthesizer.
作者
代传堂
DAI Chuantang(The 38th Research Institute of CETC,Hefei 230088,China)
出处
《电波科学学报》
EI
CSCD
北大核心
2018年第6期746-751,共6页
Chinese Journal of Radio Science
作者简介
联系人:代传堂(1981—),男,安徽人,中国电子科技集团公司第三十八所高级工程师,研究方向为频率合成及雷达收发技术.E-mail:23507207@qq.com
