摘要
随着CMOS工艺缩减至纳米尺寸,锁存器对空间辐射环境中高能粒子引起的软错误越发敏感.为缓解软错误对锁存器电路的影响,提出一种基于45 nm CMOS工艺的单粒子翻转自恢复的低功耗锁存器.该锁存器使用3个C单元构成内部互锁的结构,每个C单元的输出节点的状态由另2个C单元的输出节点决定;任意C单元的输出节点发生单粒子翻转后,该锁存器将通过内部互锁的反馈路径将翻转节点恢复正确;在瞬态脉冲消散后没有节点处于高阻态,提出的锁存器适用于采用了时钟门控技术的低功耗电路.大量的SPICE仿真结果表明,与已有的加固锁存器相比,文中提出的锁存器在延时、功耗、面积开销和软错误加固能力上取得了良好的平衡,平均节省57.53%的面积-功耗-延时积开销;详尽的蒙特卡洛仿真实验表明,该锁存器对工艺、供电电压和温度的波动不敏感.
As CMOS technology scaling down in the nanometer region,latch circuits are becoming more sensitiveto soft errors induced by energetic particles in space radiation environment.To mitigate the effects of soft errorson the latch circuits,a single event upset(SEU)resilient and low cost hardened latch design is proposed in45nmCMOS technology.The proposed latch utilizes three C-elements to form an interlocked structure in which theoutput state of each C-element is determined by the output of the other two C-elements;when the output node ofany C-element is affected by an SEU,the proposed latch will bring the affected node back to the correct statethrough interlocked feedback paths;no node exhibits a high impedance state after the transient faults die down,thus the proposed latch is suitable for a low power circuit with clock gating.Extensive SPICE simulation resultsdemonstrate that the proposed latch provides a better tradeoff among delay,power,area and soft error toleranceand saves57.53%area-power-delay-product on average in comparison with previous latches;detailed MonteCarlo simulation results indicate that the proposed latch features less sensitive to process,temperature and voltagevariations.
作者
梁华国
李昕
王志
黄正峰
Liang Huaguo;Li Xin;Wang Zhi;Huang Zhengfeng(School of Electronic Science & Applied Physics, Hefei University of Technology, Hefei 230009;Hefei Core Storage Electonic Limited, Hefei 230000)
出处
《计算机辅助设计与图形学学报》
EI
CSCD
北大核心
2017年第8期1549-1556,共8页
Journal of Computer-Aided Design & Computer Graphics
基金
国家自然科学基金(61574052
61674048)
关键词
单粒子翻转
软错误
C单元
瞬态故障
自恢复
single event upset
soft errors
C-element
transient fault
self-recovery
作者简介
梁华国(1959—),男,博士,教授,博士生导师,CCF高级会员,主要研究方向为内建自测试、数字系统设计自动化、ATPG算法、分布式控制;李昕(1995—),女,硕士研究生,主要研究方向为数字集成电路的硬件容错;王志(1988—),男,硕士,主要研究方向为数字集成电路的硬件容错;黄正峰(1978—),男,博士,副教授,硕士生导师,CCF会员,论文通讯作者,主要研究方向为数字集成电路的硬件容错、星载SoC芯片的抗辐射加固等(huangzhengfeng@139.com)
