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语音识别中卷积神经网络的FPGA实现 被引量:6

FPGA Implementation of Convolutional Neural Network in Speech Recognition
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摘要 针对应用于语音识别中的卷积神经网络,为了提高能耗比,将网络在FPGA中进行定制化实现,并通过PCIe完成了FPGA与主机的交互.对该网络定点仿真结果表明,整体采用16位定点计算可以在保证精度的情况下有效地减少数据存储量和带宽要求.采用多种复用方式进行卷积层与全连接层的速度优化,并与流水线结构相结合,提高系统了的吞吐率,在系统150 MHz的时钟频率下达到了3 715fps的速度. A convolutional neural network used in speech recognition is customized in FPGA in order to improve the energy efficiency.PCIe is used to transfer data between the FPGA and PC.A 16-bit fixed data quantization is adopted after analysis and simulation.A variety of data multiplexing methods is used for speed optimization in convolutional layer and fully-connected layer.Pipe-line helps to improve the throughput of the system.This FPGA programs with 150 MHz frequency and achieves the speed of 3715 fps.
作者 屈家丽 贺光辉 王国兴 OU Jia-li;HE Guang-hui;WANG Guo-xing(School of Electronic Information and Electrical Engineering,Shanghai Jiao Tong University,Shanghai 200240,China)
出处 《微电子学与计算机》 CSCD 北大核心 2018年第9期37-41,46,共6页 Microelectronics & Computer
关键词 语音识别 卷积神经网络 现场可编程门阵列 硬件加速 speech recognition convolutional neural network FPGA hardware acceleration
作者简介 屈家丽 女,(1993-),硕士研究生.研究方向为数字电路.E-mail:qujiali@sjtu.edu.cn.;贺光辉 男,(1980-),博士,副研究员.研究方向为通信系统、VLSI、硬件加速等.;王国兴 男,(1975-),博士,副教授.研究方向为生物医疗电子、集成电路设计.
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