摘要
Ser Des作为光纤通信系统的物理层,主要完成对光纤中传输的数据进行并行化处理和解串的功能,对整个通信系统的性能有很大影响。本文介绍10.3125Gbps Ser Des的电路结构,对高速串行接口技术进行了研究。提出了一种基于Jitter Clean锁相环结构的Ser Des设计方案,并重点研究了Ser Des核心部分如低噪声锁相环、复合式驱动器、判决反馈均衡器等设计。Ser Des IP的发射端与接收端设计了内建自测试电路能够更容易地对芯片进行功能验证,并有效检测到Ser Des内部重要模块的工作情况。锁相环是Ser Des中的重要模块,主要作用是产生片内高速时钟,将低速并行数据串化为高速串行数据,同时也可以为接收链路中的时钟数据恢复电路提供参考时钟。设计了10.3125GHz低噪声锁相环适用于10.3125Gbps Ser Des,设计中锁相环采用对电源的噪声有极高抑制且产生极低抖动的电压控制振荡器。设计采用复合式结构驱动器,在考虑速度、功耗的前提下,通过设计结合CML和VML实现操作速度在10.3125Gbps。最后,采用UMC 40nm LP 1P8M低功耗CMOS工艺实现了Ser Des芯片的版图设计并流片,Serdes IP的面积为1.08*0.74mm2,经过对封装后的Ser Des芯片进行测试,证明了该芯片能够实现内建自测试及数据传输功能。本文的目标为设计一款符合IEEE802.3 10GBASE-Kr协议的Serdes。采用1.1V、2.5V双电源电压设计了一个多速率的Ser Des发送模块,该设计可以支持1.25、2.5、5、10.3125Gbps等速率。对Ser Des电路高速差分信号的抖动、误码率和眼图各方面进行有效的功能验证和测试是非常必要的。在最快速率的10.3125Gbps模式下,单端输出波形眼图的睁开的幅度有525m V,而总体抖动只有16.34ps,10.3125Gbps速率下误码率低于10-12,动态功耗为150m W。
As the physical layer of optical fiber communication system, SerDes is used to serialize or deserilaze the data transmission in the optical fiber and has great influence on the performance of the whole communication system. In this paper, the structure of 10.3125Gbps serializer/deserializer （ SerDes ）was introduced and then the basic prin- ciple of the high-speed serial interface technology was studied. A scheme of SerDes based on the structure of jitter clean noise phase-locked loop （ PLL ） is proposed. And then, design of the core models such as low noise PLL, hy- brid-mode driver and decision-feedback equalizer are discussed. A build-in serf-test circuit was designed in the transmitter and receiver of SerDes IP to verify the function and to detect the important modules in the SerDes effec- tively. PLL is the key module of the SerDes, and used to generate high-speed clock to convert the low-speed parallel data to serial data stream and providing reference clock to the CDR of receiver. A 10.3125GHz low PLL was designed and applied to the 10.3125Gbps SerDes. The High PSRR Low jitter VCO was applied to the PLL. This design adopts hybrid-mode driver to reach 10.3125Gbps by using both CML and VML cells under sufficiently considering the speed and power consumption. The SerDes chip is implemented by using UMC Low Power 40nm 1P8M CMOS process, the area of the Serdes IP is 1.08＊0.74mm2. After testing the packaged SerDes chip could work in both the build-in serf-test mode and the in-data transmission successfully. The goal of this project is to design a Serdes which can be satisfied with IEEE802.3 10GBASE-Kr protocol. This paper introduces the design of a multi-rate SerDes transmitter which adopts 1.1V, 2.5V supply voltage and can support 1.25,2.5,5 and 10Gbps date rate. Functional verification and testing focused on jitter, bit error rate and eye diagram to the high-speed differential signal of the Serdes circuit are indispensable. In the fastest 10.3125Gbps rate mode, the output single-ended eye open of the eye diagram can reach 542mV, while the total jitter is only 16.34 ps. The power consumption is 150mW under 10.3125Gbps mode and the BER is below 10^-12.
出处
《中国集成电路》
2016年第9期28-37,76,共11页
China lntegrated Circuit
作者简介
陈宏铭，博士，技术总监，就职于智原科技（上海）有限公司，主要研究方向为数模混合电路与SoC集成设计。
林颖甫，硕士，资深研发经理，就职于智原科技有限公司，主要研究方向为高速模拟电路设计。
陈昱志，硕士，资深工程师，就职于智原科技有限公司，主要研究方向为高速低抖动16Gbps发射机、稳压器和时钟校准。
林于恒，硕士，资深工程师，就职于智原科技有限公司，主要研究方向为高速低抖动16Gbps电压模式发射机以及多功能时钟校准。
林致煌，硕士，资深工程师，就职于智原科技有限公司，主要研究方向为接收端前端设计与均衡算法。
