期刊文献+

Multi-bit soft error tolerable L1 data cache based on characteristic of data value

Multi-bit soft error tolerable L1 data cache based on characteristic of data value
在线阅读 下载PDF
导出
摘要 Due to continuous decreasing feature size and increasing device density, on-chip caches have been becoming susceptible to single event upsets, which will result in multi-bit soft errors. The increasing rate of multi-bit errors could result in high risk of data corruption and even application program crashing. Traditionally, L1 D-caches have been protected from soft errors using simple parity to detect errors, and recover errors by reading correct data from L2 cache, which will induce performance penalty. This work proposes to exploit the redundancy based on the characteristic of data values. In the case of a small data value, the replica is stored in the upper half of the word. The replica of a big data value is stored in a dedicated cache line, which will sacrifice some capacity of the data cache. Experiment results show that the reliability of L1 D-cache has been improved by 65% at the cost of 1% in performance. Due to continuous decreasing feature size and increasing device density, on-chip caches have been becoming susceptible to single event upsets, which will result in multi-bit soft errors. The increasing rate of multi-bit errors could result in high risk of data corruption and even application program crashing. Traditionally, L1 D-caches have been protected from soft errors using simple parity to detect errors, and recover errors by reading correct data from L2 cache, which will induce performance penalty. This work proposes to exploit the redundancy based on the characteristic of data values. In the case of a small data value, the replica is stored in the upper half of the word. The replica of a big data value is stored in a dedicated cache line, which will sacrifice some capacity of the data cache. Experiment results show that the reliability of L1 D-cache has been improved by 65% at the cost of 1% in performance.
出处 《Journal of Central South University》 SCIE EI CAS CSCD 2015年第5期1769-1775,共7页 中南大学学报(英文版)
基金 Projects(61472322,61272122)supported by the National Natural Science Foundation of China Project(3102014JSJ0001)supported by the Fundamental Research Funds for the Central Universities,China Project(2013JQ8034)supported by the Natural Science Foundation of Shaanxi Province,China Project(JC20120239)supported by the Basic Research Foundation of NWPU,China
关键词 data cache RELIABILITY REPLICA data value single event upset(SEU) data cache reliability replica data value single event upset (SEU)
作者简介 Corresponding author: WANG Dang-hui, PhD, Associate Professor; Tel: +86-29-88431557; E-mail: wangdh@nwpu.edu.cn
  • 相关文献

参考文献19

  • 1SYED Z S, MEHDI B T. Transient error detection and recovery in processor pipelines [C]// 24tb IEEE Int'l Symp on Defect Fault Tolerance in VLSI Systems. Chicago, Illinois, USA: IEEE Computer Society, 2009:304 312.
  • 2DEGALAHAL V, VIJAYKRISHNAN V, IRWIN M J. Analyzing soft errors in leakage optimized SRAM design [C]// 16th Int'l Conf on VLSI Design. New Delhi, India: IEEE Circuits and Systems Society, 2003: 227-233.
  • 3ZHANG Wei. Computing cache vulnerability to transient rrrors and its implication [C]//24th IEEE Int'l Symp on Defect Fault Tolerance in VLSI Systems. Monterey, California, USA: IEEE Computer Society, 2005: 427-435.
  • 4BHATTACHARYA K, RANGANATHAN N, K1M S. A framework for correction of multi-bit soft errors in L2 caches based on redundancy [J]. IEEE Trans on VLSI, 2009, 17(2): 194-206.
  • 5Sun Ultra Sparc T3. [Online]. [2010-07] Available: http://www.sun.com/processors/whitepapers.
  • 6WANG Dang-hui, XIN Ming-rui. Design of a reliable cache based on grouped checking and data reloading. [C]//Proc of the 2nd Int'l Conf on Information Science and Engineering. Hangzhou, China: IEEEComputer Society, 2010:5051-5054.
  • 7PAUL S, CAI F, ZHANG X M, BHUNIA S. Reliability-driven ECC allocation for multiple bit error resilience in processor cache [J]. IEEE Trans on Computers, 2011, 60(1): 20-34.
  • 8WANG S, HU J, ZIAVRAS S G. Replicating tag entries for reliability enhancement in cache tag arrays [J]. IEEE Trans on Very Large Scale Integeration (VLSI) Systems, 2011, 20(4): 643-654.
  • 9成玉,马安国,王永文,唐遇星,张民选.SS-SERA:An improved framework for architectural level soft error reliability analysis[J].Journal of Central South University,2012,19(11):3129-3146. 被引量:2
  • 10ZHANG Wei, GURUMUTHI S, KANDEMIR M, SIAVASUBRAMANIAM A. ICR: in-cache replication for enhancing data cache reliability [C]//Proc lnt'l Conf Dependable Systems and Networks (DSN), San Francisco, California, USA: IEEE Computer Society, 2003: 291-300.

二级参考文献26

  • 1LI B, DUAN L, PENG L. Efficient microarchitectural vulnerabilities prediction using boosted regression trees and patient rule inductions [J]. IEEE Transactions on Computers, 2010, 59(5): 593-607.
  • 2WANG S, HU J, ZIAVRAS S G. On the characterization and optimization of on-chip cache reliability against soil errors [J]. IEEE Transactions on Computers, 2009, 58(9): 1171-1184.
  • 3WANG S, I-IU J, ZIAVRAS S G Self-adaptive data caches for soft-error reliability [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008, 27(8): 1503-1507.
  • 4ERGIN O, UNSAL O S, VERA X, GONZALEZ A. Reducing soft errors.through operand width aware policies [J]. IEEE Transactions on Dependable and Secure Computing, 2009, 6(3): 217-230.
  • 5YOON D H, EREZ M. Memory mapped ecc: low-cost error protection for last level caches [C]// Proceedings of 36th International Symposium Computer Architecture. New York, NY, USA: ACM, 2009: 116-127.
  • 6YOON D H, EREZ M. Virtualized and flexible ECC for main memory [C]// Proceedings of the 15th Architectural Support for Programming Languages and Operating Systems. New York, NY, USA: ACM, 2010: 397-408.
  • 7KIM S. Reducing area overhead for error-protecting large L2L3 caches [J]. IEEE Transactions on Computers, 2009, 58(3): 300-310.
  • 8SRIDHARAN V, ASADI H, TAHOORI M, KAELI D. Reducing data cache susceptibility to soft errors [J]. IEEE Transactions on Dependable and Secure Computing, 2006, 3(4): 353-364.
  • 9MUKHERJEE S S, WEAVER C, EMER J, RE1NHARDT S, AUSTIN T. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor [C]// Proceedings of the International Symposium on Microarchitecture. Washington D C, USA: IEEE Computer Society, 2003: 29-40.
  • 10WANG N J, QUEK J, RAFACZ T M, PATEL S J. Characterizing the effects of transient faults on a high-performance processor pipeline [C]// Proceedings of the International Conference on Dependable Systems and Networks. Piscataway, N J, USA: IEEE, 2004: 61-70.

共引文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部