摘要
在自适应滤波算法中,空域递推最小二乘(RLS)算法以其较快的收敛速度以及能计算出精确的最佳滤波器系数等优势得到了广泛的运用。但是由于该算法较为复杂,计算量大,因此硬件实现时耗费资源多,难度大。提出了一种任意维空域递推最小二乘算法的FPGA(现场可编程门阵列)实现的方法,该方法可以在硬件结构中使用较少的乘法器和寄存器进行任意维空域递推最小二乘运算,从而解决维数变多后资源不够用的问题。
Abstract ：Among all the adaptive filtering algorithms, RLS is widely applied for its fast convergence rate and precise calculation of the filter coefficients. However, due to its complexity and large computation, the hard- ware implementation of RLS would bring many difficulties and consume a lot of resources. This paper proposes a method that could implement the RLS algorithm with any dimension in FPGA（Field Progrmmnable Gate Ar-ray） and solve the problem in lacking resources due to less multipliers and registers in hardware construction.
出处
《通信技术》
2015年第6期746-749,共4页
Communications Technology
作者简介
幸璐璐（1981-），女，硕士，工程师，主要研究方向为卫星通信抗干扰理论研究与设计。
