摘要
针对Virtex-5 FXT系列FPGA中具有两个PowerPC440嵌入式处理器内核的特点,文中提出一种"主-从"异构式控制模型架构的嵌入式雷达控制器设计方法。该方法采用FC、sRIO等高速串行传输技术提高了控制器接口带宽,并通过预先任务规划,充分发挥了两个PowerPC处理器的性能,设计成本与已有解决方案相比显著降低。应用表明,该控制器整体性能明显提高,可满足现代相控阵雷达提出的微秒级响应与吉比特级传输要求。
According to the feature of the two PowerPC440 embedded processor cores in the Virtex-5 FXT series FPGA, this paper proposes a design method of embedded radar controller which uses heterogeneous master-slave architecture. This method improves the controller interface bandwidth by using the high-speed serial transmission technology such as FC, sRIO, and gives full play to the performance of two PowerPC processors by pre-planning the task. The design cost is lowered significantly comparing with original solution. Application indicates that the overall performance of the controller was improved obviously. The performance meets microsecond response and Gbps transmission requirements of modem phased array radar.
出处
《现代雷达》
CSCD
北大核心
2014年第6期35-38,44,共5页
Modern Radar
关键词
雷达控制器
多核处理器
异构架构
非对称多处理
光纤通道
radar controller
multi-core processor
heterogeneous architecture
asymmetric multiprocessing
fiber channel
作者简介
通信作者：施海峰.Email：damaoniu1977@163．com. 施海锋 男，1977年生，高级工程师。研究方向为嵌入式控制系统、高速总线技术的设计与应用。
柏玉娴 女，1981年生，工程师。研究方向为嵌入式控制系统、实时操作系统的设计与应用等。
