摘要
随工艺的演进,集成电路发展已经进入超深亚微米阶段,芯片的成本、性能、功耗、信号完整性等问题将成为制约SOC芯片设计的关键问题。文章基于65GP工艺的实际项目模块级物理设计,在现超深亚微米下,对芯片的低功耗、congestion、信号完整性等后端物理设计等关键问题进行了细致研究,并提出了一些新方法和新思想,从而提高了signoff的交付质量,完成了tapeout要求。
With the evolution of process, the development of integrated circuit has turned into ultra-deep submicron stage. Some problems such as the cost, performance, power consumption, signal integrity have become the critical issues in SOC （system on chip） design. Based on the module level physical design of 65GP technology in practical program, and in ultra-deep submicron, some key problems in the back-end of physical design of the chip are studied in detail, such as low-cost, congestion and signal integrity. Some new methods and new ideas are put forward, thus the delivery quality of sign off is improved and satisfied the requirements of tapeout.
出处
《物联网技术》
2013年第8期59-63,共5页
Internet of things technologies
关键词
65GP
低功耗
拥塞
信号完整性
签核
65GP
low power consumption
congestion
signal integrity
sign off
作者简介
沈良伟 1988年出生，电子科技大学微电子学与固体电子学专业研究生。研究方向为超高速集成电路。
