摘要
由于能够获得更优异的数据传输性能,高速串行传输方式正逐步替代并行传输方式成为主流。采用高速串行LVDS信号形式传输能够减少器件I/O管脚数目,提高芯片集成度,得到了越来越多的芯片厂商的支持。同时,现场可编程门阵列(FPGA)功能越来越强大,受到了广大电子技术开发人员的青睐,其中SelectIO技术为FPGA实现高速数据传输提供了良好的平台。针对ADC输出的8通道12位高速串行LVDS信号,利用SelectIO专用逻辑资源,提出了基于XILINX Virtex-6FPGA的解串器逻辑电路。实验结果表明,所设计的电路能够完成LVDS串行信号至并行信号的转换,实现多通道高速串行LVDS数据在FPGA内的接收。
As a result of superior performance in data transmission,high-speed serial transmission method is gradually instead of parallel transmission and becoming the main stream. The output of high-speed serial LVDS has a variety of advantages,such as reducing the number of chip IO, improving the integration of chip and so on, and more and more manufacturers＇ products support this technique. Furthermore craigslist, FPGA is increasingly powerful and the technique of SeleetIO provides a great platform for FPGA to realise high-speed data transmission. For 8 channels, 12 bits high-speed serial LVDS signals from ADC, this paper proposes a method to design deserializer based on XlLINX Virtex 6 FPGA with SelectlO. The proposed deserializer completes the conversion from LVDS serial signal to parallel signal and the receiving of multi-channel high-speed serial LVDS data with FPGA.
出处
《电子测量技术》
2013年第4期63-67,83,共6页
Electronic Measurement Technology
