摘要
经典多级结构的数字抽取滤波器占用系统大量的功耗与面积资源,文章设计的改进型64倍降采样数字抽取滤波器采用由级联积分梳状滤波器、补偿FIR滤波器和半带滤波器组成,在保持Σ-ΔADC转换精度的约束下,实现了最大程度降低系统功耗与面积的设计目标。在多级级联积分梳状(CIC)滤波器的设计中,充分运用置换原则以优化各级级数并采用非递归结构实现方式,同时将多相结构运用到补偿滤波器与半带滤波器中,获得电路功耗与面积的明显降低。将Σ-Δ调制器输出信号作为测试激励,通过Matlab系统仿真、FPGA验证与FFT信号分析,得到的输出数据信噪比达到15bit有效位数精度,且系统速度满足要求。
A digital filter used in sigma delta ADC is designed in this thesis.It adopts multi-stage structure,and is composed of CIC filter,compensation filter and halfband filter.Meanwhile,commutative rules are fully used and combed filter has also used multi-stage structure.It is implemented by non-recursive structure to more greatly reduce area and power consumption,compared to classical one.Polyphase structure is used by compensation and halfband filter to further reduce power consumption.Output of sigma delta modulator is used as the test input of digtal filter.It meets SNR requirements after Matlab system simulation,FPGA verification and FFT analysis.
出处
《电子与封装》
2010年第8期21-26,共6页
Electronics & Packaging
作者简介
梅海军（1971-），男，浙江人，西安电子科技大学毕业，工程师，现从事集成电路制造和设计。
