摘要
针对调试的可移植性,建立同流水相关的精确调试异常模型,模型通过增加调试中断、单步、软硬件断点等精确调试异常的产生和处理机制、片外调试存储空间以及基于JTAG(joint test action group)的快速通信协议,实现一种通过JTAG接口的嵌入式处理器核的片上调试方案.该调试模型在嵌入式处理器RISC32E核的应用实现表明,它具有良好的可观察性和可控制性,并且该模型的应用不局限于六级流水结构的微处理器,还可以方便地推广到其他流水结构的微处理器.对比调试过程中的一些基本调试操作开销,该调试方案具有较高的调试效率.
A general precise debug exception model based on pipeline was established with portability,which provides a strategy for on-chip debug by adding generation and processing mechanism of precise debug exceptions,such as debug interrupt,step,hardware/software breakpoints,etc.,in addition of a segment of off-chip debug memory and a fast transfer method through joint test action group（JTAG） port. The implementation of the proposed model on an embedded processor RISC32E shows that it meets the requirements of observability and controllability. The above description should not be taken as limiting the utilization of the model which is defined by the six-pipeline microprocessor. The model can be easily transplanted onto other microprocessors which have various modifications of pipeline. The proposed strategy has great efficiency of debugging in the case of comparison of some basic debugging operation overhead.
出处
《浙江大学学报（工学版）》
EI
CAS
CSCD
北大核心
2010年第6期1067-1072,共6页
Journal of Zhejiang University：Engineering Science
关键词
片上调试
JTAG
可观察性
可控制性
on-chip debug
joint test action group （JTAG）
observability
controllability
作者简介
刘鹏（1970-），男，陕西铜川人，副教授，主要从事计算机体系结构、集成电路设计和并行处理等研究E—mail：liupeng@zju．edu．cn
