摘要
针对低密度奇偶校验码(简称LDPC码)的直接编码运算量较大、复杂度高,根据Richardson和Urbanke(RU)建议的编码方案,介绍一种适于在FPGA上实现,利用有效校验矩阵来降低编码复杂度的LDPC编码方案,给出了编码器设计实现的原理和编码器的结构和基本组成。在QuartusⅡ7.2软件平台上采用基于FPGA的VHDL语言实现了有效的编码过程。结果表明:此方案在保证高效可靠传输的同时降低了实现的复杂度。这种编码方案可灵活应用于不同的校验矩阵H,码长和码率的系统中。
According to Richardson and Urbanke （RU） the proposed encoding scheme for the large computing and the high complexity of the direct encoding large amount of the low-density parity-check codes （LDPC codes）, this paper presents a flexible LDPC encoding scheme suitable for FPGA by using effective check matrix to reduce the complexity of the encoding. It gave- the design and implementation principles of encoder and structure and basic components. The effective encoding process based on FPGA with VHDL language is implemented on Quartus Ⅱ 7.2 software platform, the results show that：this scheme decreases the implementation complexity while maintaining efficient and reliable transmission. The encoder suits different parity check H matrix, rates and block length.
出处
《电子设计工程》
2010年第4期102-104,共3页
Electronic Design Engineering
作者简介
张建光（1982-），男，河北邯郸人，硕士研究生。研究方向：光电信息处理及软件。
