摘要
在分析DDRSDRAM基本特征的基础上,按照JEDEC DDR SDRAM规范提出了一个详细的DDR SDRAM控制器的设计方案。该方案采用Verilog HDL硬件描述语言实现,集成到高速SoC芯片中,然后使用Synopsys VCS对该控制器进行仿真,并在Stratix-Ⅱ开发板进行了FPGA验证。在阐述该控制器设计原理的基础上,进行模块划分和具体设计,提出了高效、稳定的处理方案,最后通过仿真和FPGA验证确保了设计的正确性。
This thesis makes an analysis of the basic characteristics of DDR SDRAM first,and puts forward a detailed solution of DDR SDRAM controller design based on JEDEC DDR SDRAM specification . The controller is implemented by Verilog HDL hardware description language and integrated into a high performance SoC. The simulation is conducted by Synopsys VCS, and the controller also passes FPGA verification using a Stratix-Ⅱ development board. This thesis sets out to explain the design principles, module partition, detailed design, and provides an efficient and robust solution. Finally, the design passes simula- tion and FPGA verification.
出处
《电子器件》
CAS
2009年第3期592-595,600,共5页
Chinese Journal of Electron Devices
作者简介
朱炜（1985-），男，硕士研究生，从事数字集成电路前端设计，zhuweilion@hotmail．com；
刘新宁（1977-），男，讲师，从事数字集在电路前端设计
