摘要
流水线技术是FPGA设计速度优化的有效方法之一。通过不同流水线级数和不同位宽的加法器和乘法器综合数据的对比,说明在用FPGA实现数字信号处理硬件化运算中流水线技术的有效性和选择方法。对流水线应用中设计方法的选择、流水线首次延时和寄存器触发时间、嵌入式存储器块的使用、控制流水线和数据流水线的划分等需要注意的关键问题进行了简要分析。
Pipeline technology is one of the valid speed optimizing methods for FPGA design.By contrasting the compiler data for adders and multipliers with different pipeline series and different data widths, the pipeline technology＇s validity for digital signal processing operation in harden way is illuminated and the selecting method is indicated too. Some pivotal problems must pay attention to in pipeline design such as the selecting for design method, the first latency of Pipeline and the trigger time of register, the usage for embedded memory, the partition for controlling pipeline and data pipeline are analyzed briefly.
出处
《电子技术（上海）》
2009年第6期62-64,共3页
Electronic Technology
基金
泰山学院重点科研项目(编号:060102)
关键词
流水线技术
DSP运算
数据吞吐率
参数可设置宏单元
Pipeline Technology, DSP Operation, Data Throughput, Library of Parameterrized Modules （LPM） .
作者简介
王春玲泰山学院物理与电子工程学院副教授／硕士主要研究方向：EDA技术，测控技术。
