摘要
在混合信号系统芯片设计过程中,复杂的全芯片系统验证以及数字单元和模拟IP电路间的接口节点分析成为设计的瓶颈.提出一种基于NanoSim-VCS的混合信号验证方法,以SHU-MV06芯片为具体对象,对一个包括Verilog和SPICE的数模混合系统设计进行验证.这一验证方法在仿真的速度和精度间进行折衷,在保证一定精度的基础上大大缩短了仿真时间,提高了验证效率,使设计人员在早期仿真阶段就能及时发现设计中的问题,改进了设计质量.采用此方法验证的数模混合系统级芯片SHU-MV06一次流片成功,表明了此方法的正确性和有效性.
Complex full-chip system verification and interface nodes analysis between analog and digital circuit are a bottle-neck in mixed-signal system design. In this paper, a mixed-signal verification method based on NanoSim-VCS is proposed, which is used to verify SHU-MV06, a mixed-signal design including Verilog and SPICE. This method provides efficient simulation with high accuracy and speed by performing speed-versus-accuracy tradeoffs. Defects can be found in time at an early stage and the design quality can be improved significantly.
出处
《上海大学学报（自然科学版）》
CAS
CSCD
北大核心
2009年第1期42-46,共5页
Journal of Shanghai University:Natural Science Edition
基金
上海市科委集成电路设计专项资助项目(077062008)
作者简介
通信作者：胡越黎（1959～），男，教授，博士，研究方向为图像处理、MCU设计等．E-mail：huyueli@shu．edu．cn
