摘要
提高指令级并行度是微处理器体系结构发展的重要方向,也是开发基于FPGA的高性能微处理器的重要内容之一。本文论述了一个基于FPGA的流水线微处理器的指令流水线结构和系统设计,针对在指令流水执行过程中出现的相关问题,提出了相应的检查算法及解决方法。通过一个典型程序对流水线微处理器功能进行仿真,其运行结果表明此微处理器的最大吞吐率为一个时钟周期解释完一条指令,证实了流水线微处理器设计的正确性和高性能。该微处理器的设计在开发未来具有微处理功能的专用集成电路设计方面具有较高的实用价值。
Improving the degree of the instruction level parallelism is not only an important development trend in microprocessor architecture but also a significant content of exploiting high performance microprocessor based on FPGA. This paper discusses instruction pipeline structure and system design of pipeline microprocessor based on FPGA. The dependence checking algorithms and their resolving methods are brought up in this paper to settle dependence problem happening in the pipeline executing of instructions. By simulating to run a concrete program on this pipeline microprocessor, the result shows that the biggest throughput rate of this microprocessor is a clock cycle for explaining an instruction, which has confirmed the pipeline microprocessor to be of accuracy and high performance. The design of this microprocessor will have a high practical value in developing special-purpose integrated circuit which has micro-processing function in the future.
出处
《微计算机信息》
2009年第5期173-175,共3页
Control & Automation
作者简介
陈智勇（1971-），男，湖北潜江人，硕士．副教授，主要研究方向：计算机网络与系统结构。通讯地址：（541004 广西广西桂林市桂林电子科技大学计算机与控制学院）
