摘要
研究了超高速(10Gb/s)NRZ码时钟数据恢复电路的行为级建模,并采用TSMC 0.18μm CMOS工艺进行了电路级仿真。
A PLL （ phase-locked loop ） -type clock and data recovery circuit is studied by using a behavior model. The model is validated by circuit simulation with TSMC 0. 18 μm CMOS technology.
出处
《中国集成电路》
2008年第9期27-31,共5页
China lntegrated Circuit
关键词
时钟数据恢复
锁相环
行为模型
电路仿真
Clock and data recovery
phase-locked loop
behavior model
Circuit simulation
