摘要
介绍一种提高直接数字合成器(DDS)系统时钟频率的并行处理方法。给出了一个基于现场可编程门阵列(FPGA)的具有400MHz系统时钟频率DDS电路的实现方法和实验测试结果。采用直接中频输出方式,输出频率范围250MHz～350MHz,频率分辨率6Hz,寄生信号抑制50dB。该DDS电路具有接口简单、使用灵活等优点,可用于雷达、电子战领域的宽带信号产生。
A method of the parallel processing techniques was introduced to increase the direct digital synthesizer（DDS） system clock frequency. The realization methods and the experimental results of a filed programmable gate array （FPGA）-based DDS circuit with a system clock frequency of 400MHz were given. In this circuit, the direct intermediate output method was used, the output signal frequency range, frequency resolution and spurious suppression were 250MHz～350MHz, 6Hz and 50dB respectively. This DDS circuit have the advantage of simple to interface, flexible to use and can be used in wide bandwidth signal production in the field of radar and electronic warfare.
出处
《电子技术应用》
北大核心
2007年第10期41-43,48,共4页
Application of Electronic Technique
