摘要
维特比译码器是广泛使用的极大似然解码方法。该文提出了有别于IEEE802.11a标准的解码方法,将软判决译码使用在该标准卷积码的解码机制上,利用算术部件的重组和混合向后追溯式以及时钟关断技术,在保证性能和低复杂度前提下减少存储器读写操作以降低功耗,利用SMIC0.18μmCMOS工艺设计实现该译码器,在ALTERAFPGA上实现原型验证,性能满足IEEE802.11a标准要求。
Viterbi algorithm is a widely used maximum likelihood estimating method. A modified algorithm is proposed to improve the decoding performance with soft-decision estimation based on IEEE 802.11a specification. The methods of re-arranging add-compare-select units, hybrid trace-back and clock gating are used to reduce operations and power. Simulation results indicate that both hardware complexity and power dissipation can be reduced but with same performance. The ASIC design is achieved under the process of SMIC 0.18μm, photo-typed in FPGA Cyclone of ALTERA.
出处
《计算机工程》
CAS
CSCD
北大核心
2007年第9期243-245,共3页
Computer Engineering
作者简介
金文学（1979-），男，硕士生，主研方向：数字集成电路设计；E-mail：jinwx@szicc.com.cn.
刘秉坤，硕士生；
陈岚，博士、研究员.
